Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator

Chulwoo Kim; In Chul Hwang; Sung Mo Kang

Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator

Chulwoo Kim^*
, In Chul Hwang
, Sung Mo Kang

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

3 Citations (Scopus)

Abstract

A 1 GHz DLL-based clock generator in 0.35 μm CMOS occupies 0.08 mm². It has fast locking time and no jitter-accumulation problem. A phase detector with reset circuitry and a frequency multiplier overcome the limited locking range and frequency multiplication problem of conventional DLL-based systems, Measured peak-to-peak jitter is ±7.28 ps.

Original language	English
Pages (from-to)	106-107+423
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Issue number	SUPPL.
Publication status	Published - 2002
Externally published	Yes
Event	2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States Duration: 2002 Feb 3 → 2002 Feb 7

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@article{5b474f142b0949f6bc35c9aaa3a7729d,

title = "Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator",

abstract = "A 1 GHz DLL-based clock generator in 0.35 μm CMOS occupies 0.08 mm2. It has fast locking time and no jitter-accumulation problem. A phase detector with reset circuitry and a frequency multiplier overcome the limited locking range and frequency multiplication problem of conventional DLL-based systems, Measured peak-to-peak jitter is ±7.28 ps.",

author = "Chulwoo Kim and Hwang, \{In Chul\} and Kang, \{Sung Mo\}",

year = "2002",

language = "English",

pages = "106--107+423",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "SUPPL.",

note = "2002 IEEE International Solid-State Circuits Conference ; Conference date: 03-02-2002 Through 07-02-2002",

}

TY - JOUR

T1 - Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator

AU - Kim, Chulwoo

AU - Hwang, In Chul

AU - Kang, Sung Mo

PY - 2002

Y1 - 2002

N2 - A 1 GHz DLL-based clock generator in 0.35 μm CMOS occupies 0.08 mm2. It has fast locking time and no jitter-accumulation problem. A phase detector with reset circuitry and a frequency multiplier overcome the limited locking range and frequency multiplication problem of conventional DLL-based systems, Measured peak-to-peak jitter is ±7.28 ps.

AB - A 1 GHz DLL-based clock generator in 0.35 μm CMOS occupies 0.08 mm2. It has fast locking time and no jitter-accumulation problem. A phase detector with reset circuitry and a frequency multiplier overcome the limited locking range and frequency multiplication problem of conventional DLL-based systems, Measured peak-to-peak jitter is ±7.28 ps.

UR - https://www.scopus.com/pages/publications/0036230219

UR - https://www.scopus.com/pages/publications/0036230219#tab=citedBy

M3 - Conference article

AN - SCOPUS:0036230219

SN - 0193-6530

SP - 106-107+423

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

IS - SUPPL.

T2 - 2002 IEEE International Solid-State Circuits Conference

Y2 - 3 February 2002 through 7 February 2002

ER -

Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator

Abstract

ASJC Scopus subject areas

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