Low-power small-area ±7.28ps Jitter 1GHz DLL-based clock generator

Chulwoo Kim; In Chul Hwang; Sung Mo Kang

Low-power small-area ±7.28ps Jitter 1GHz DLL-based clock generator

Chulwoo Kim, In Chul Hwang, Sung Mo Kang

Research output: Contribution to journal › Conference article › peer-review

Abstract

Low-power small area±7.28 ps jitter 1 GHz delay locked loop (DLL)-based clock generator was discussed. For an open-loop VCDL, the jitter is reported to accumulate only within a single delay line. With a high-Q crystal oscillator, the DLL-based clock generator produced a clean clock signal. Delay was adjusted by controlling the supply voltage with a linear voltage regulator.

Original language	English
Pages (from-to)	142-143+453+123
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication status	Published - 2002
Externally published	Yes
Event	2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States Duration: 2002 Feb 3 → 2002 Feb 7

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@article{90634a947d144f388c782a57748d1353,

title = "Low-power small-area ±7.28ps Jitter 1GHz DLL-based clock generator",

abstract = "Low-power small area±7.28 ps jitter 1 GHz delay locked loop (DLL)-based clock generator was discussed. For an open-loop VCDL, the jitter is reported to accumulate only within a single delay line. With a high-Q crystal oscillator, the DLL-based clock generator produced a clean clock signal. Delay was adjusted by controlling the supply voltage with a linear voltage regulator.",

author = "Chulwoo Kim and Hwang, {In Chul} and Kang, {Sung Mo}",

year = "2002",

language = "English",

pages = "142--143+453+123",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2002 IEEE International Solid-State Circuits Conference ; Conference date: 03-02-2002 Through 07-02-2002",

}

TY - JOUR

T1 - Low-power small-area ±7.28ps Jitter 1GHz DLL-based clock generator

AU - Kim, Chulwoo

AU - Hwang, In Chul

AU - Kang, Sung Mo

PY - 2002

Y1 - 2002

N2 - Low-power small area±7.28 ps jitter 1 GHz delay locked loop (DLL)-based clock generator was discussed. For an open-loop VCDL, the jitter is reported to accumulate only within a single delay line. With a high-Q crystal oscillator, the DLL-based clock generator produced a clean clock signal. Delay was adjusted by controlling the supply voltage with a linear voltage regulator.

AB - Low-power small area±7.28 ps jitter 1 GHz delay locked loop (DLL)-based clock generator was discussed. For an open-loop VCDL, the jitter is reported to accumulate only within a single delay line. With a high-Q crystal oscillator, the DLL-based clock generator produced a clean clock signal. Delay was adjusted by controlling the supply voltage with a linear voltage regulator.

UR - http://www.scopus.com/inward/record.url?scp=0036117640&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036117640&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0036117640

SN - 0193-6530

SP - 142-143+453+123

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - 2002 IEEE International Solid-State Circuits Conference

Y2 - 3 February 2002 through 7 February 2002

ER -

Low-power small-area ±7.28ps Jitter 1GHz DLL-based clock generator

Abstract

ASJC Scopus subject areas

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