Low-temperature electrical characterization of junctionless transistors

Dae Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu Tae Kim, Gérard Ghibaudo

Research output: Contribution to journalArticlepeer-review

76 Citations (Scopus)

Abstract

The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (μ0) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (V fb), threshold voltage (Vth) and subthreshold swing (S) of JLT devices was also discussed.

Original languageEnglish
Pages (from-to)135-141
Number of pages7
JournalSolid-State Electronics
Volume80
DOIs
Publication statusPublished - 2013

Bibliographical note

Funding Information:
This work was supported by European Union 7th Framework Program project SQWIRE under Grant Agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology ( Converging Research Center Program , 2012K001313 and Global Frontier Research Program , No. 2011-0031638 ). The authors also thank Xavier Mescot and Martine Gri for their help in operating the cryogenic probe station system.

Keywords

  • Flat-band voltage (V)
  • Implantation induced defects
  • Junctionless transistors (JLTs)
  • Scattering mechanisms
  • Threshold voltage (V)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Materials Chemistry
  • Electrical and Electronic Engineering

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