Low-temperature electrical characterization of junctionless transistors

Dae Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu Tae Kim, Gérard Ghibaudo

Research output: Contribution to journalArticlepeer-review

69 Citations (Scopus)


The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (μ0) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (V fb), threshold voltage (Vth) and subthreshold swing (S) of JLT devices was also discussed.

Original languageEnglish
Pages (from-to)135-141
Number of pages7
JournalSolid-State Electronics
Publication statusPublished - 2013


  • Flat-band voltage (V)
  • Implantation induced defects
  • Junctionless transistors (JLTs)
  • Scattering mechanisms
  • Threshold voltage (V)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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