Low-temperature electrical characterization of junctionless transistors

Dae Young Jeon; So Jeong Park; Mireille Mouis; Sylvain Barraud; Gyu Tae Kim; Gérard Ghibaudo

doi:10.1016/j.sse.2012.10.018

Low-temperature electrical characterization of junctionless transistors

Dae Young Jeon^*
, So Jeong Park
, Mireille Mouis
, Sylvain Barraud
, Gyu Tae Kim
, Gérard Ghibaudo

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

84 Citations (Scopus)

Abstract

The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (μ₀) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (V _fb), threshold voltage (V_th) and subthreshold swing (S) of JLT devices was also discussed.

Original language	English
Pages (from-to)	135-141
Number of pages	7
Journal	Solid-State Electronics
Volume	80
DOIs	https://doi.org/10.1016/j.sse.2012.10.018
Publication status	Published - 2013

Bibliographical note

Funding Information:
This work was supported by European Union 7th Framework Program project SQWIRE under Grant Agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology ( Converging Research Center Program , 2012K001313 and Global Frontier Research Program , No. 2011-0031638 ). The authors also thank Xavier Mescot and Martine Gri for their help in operating the cryogenic probe station system.

Keywords

Flat-band voltage (V)
Implantation induced defects
Junctionless transistors (JLTs)
Scattering mechanisms
Threshold voltage (V)

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Materials Chemistry
Electrical and Electronic Engineering

Access to Document

10.1016/j.sse.2012.10.018

Cite this

@article{69426887f0a44220a3a033c4cf067bde,

title = "Low-temperature electrical characterization of junctionless transistors",

abstract = "The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (μ0) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (V fb), threshold voltage (Vth) and subthreshold swing (S) of JLT devices was also discussed.",

keywords = "Flat-band voltage (V), Implantation induced defects, Junctionless transistors (JLTs), Scattering mechanisms, Threshold voltage (V)",

author = "Jeon, \{Dae Young\} and Park, \{So Jeong\} and Mireille Mouis and Sylvain Barraud and Kim, \{Gyu Tae\} and G{\'e}rard Ghibaudo",

note = "Funding Information: This work was supported by European Union 7th Framework Program project SQWIRE under Grant Agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology ( Converging Research Center Program , 2012K001313 and Global Frontier Research Program , No. 2011-0031638 ). The authors also thank Xavier Mescot and Martine Gri for their help in operating the cryogenic probe station system.",

year = "2013",

doi = "10.1016/j.sse.2012.10.018",

language = "English",

volume = "80",

pages = "135--141",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Ltd",

}

TY - JOUR

T1 - Low-temperature electrical characterization of junctionless transistors

AU - Jeon, Dae Young

AU - Park, So Jeong

AU - Mouis, Mireille

AU - Barraud, Sylvain

AU - Kim, Gyu Tae

AU - Ghibaudo, Gérard

N1 - Funding Information: This work was supported by European Union 7th Framework Program project SQWIRE under Grant Agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology ( Converging Research Center Program , 2012K001313 and Global Frontier Research Program , No. 2011-0031638 ). The authors also thank Xavier Mescot and Martine Gri for their help in operating the cryogenic probe station system.

PY - 2013

Y1 - 2013

N2 - The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (μ0) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (V fb), threshold voltage (Vth) and subthreshold swing (S) of JLT devices was also discussed.

AB - The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (μ0) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (V fb), threshold voltage (Vth) and subthreshold swing (S) of JLT devices was also discussed.

KW - Flat-band voltage (V)

KW - Implantation induced defects

KW - Junctionless transistors (JLTs)

KW - Scattering mechanisms

KW - Threshold voltage (V)

UR - https://www.scopus.com/pages/publications/84871651510

U2 - 10.1016/j.sse.2012.10.018

DO - 10.1016/j.sse.2012.10.018

M3 - Article

AN - SCOPUS:84871651510

SN - 0038-1101

VL - 80

SP - 135

EP - 141

JO - Solid-State Electronics

JF - Solid-State Electronics

ER -

Low-temperature electrical characterization of junctionless transistors

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this