Lowering minimum supply voltage for power-efficient cache design by exploiting data redundancy

Keyphrases

• 32nm Technology 33%
• Benchmark Suite 33%
• Cache Coherence 33%
• Cache Design 100%
• Cache Organization 33%
• Cache Replacement 33%
• Caching 33%
• Cycle-accurate Simulator 33%
• Data Redundancy 100%
• Dynamic Power 33%
• Dynamic Voltage Scaling 33%
• Energy Saving 66%
• Error-detecting Codes 33%
• High Complexity 33%
• High Power 33%
• L2 Cache 33%
• Large Caches 33%
• Memory Hierarchy 33%
• Minimum Power 33%
• Minimum Voltage 100%
• Multi-bit 33%
• PARSEC Benchmarks 33%
• Power Consumption 33%
• Power Efficient 100%
• Process Variation 33%
• Redundancy 33%
• Redundant Copy 66%
• Splashing 33%
• SRAM Reliability 33%
• Static Power 33%
• Voltage Scaling 100%

Computer Science

• And-States 50%
• Cache Coherence 50%
• Cache Organization 50%
• Cache Replacement Policy 50%
• Cycle-Accurate Simulator 50%
• Data Redundancy 100%
• Dynamic Power 50%
• Dynamic Voltage Scaling 50%
• Error Detection 50%
• Good Candidate 50%
• L2 Cache 50%
• Memory Hierarchy 50%
• Power Consumption 50%
• Power Efficient 100%
• Process Variation 50%
• Static Power 50%
• Supply Voltage 100%

Engineering

• Cache Coherence 25%
• Design Cache 100%
• Electric Power Utilization 25%
• Energy Engineering 25%
• Error Detection 25%
• Memory Hierarchy 25%
• Process Variation 25%
• Supply Voltage 100%
• Voltage Scaling 100%