Minimizing CMT miss penalty in selective page-level address mapping table

Ronnie Mativenga; Joon Young Paik; Junghee Lee; Tae Sun Chung; Youngjae Kim

doi:10.1109/CLUSTER.2016.81

Minimizing CMT miss penalty in selective page-level address mapping table

Ronnie Mativenga, Joon Young Paik, Junghee Lee, Tae Sun Chung, Youngjae Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.

Original language	English
Title of host publication	Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	152-153
Number of pages	2
ISBN (Electronic)	9781509036530
DOIs	https://doi.org/10.1109/CLUSTER.2016.81
Publication status	Published - 2016 Dec 6
Externally published	Yes
Event	2016 IEEE International Conference on Cluster Computing, CLUSTER 2016 - Taipei, Taiwan, Province of China Duration: 2016 Sept 13 → 2016 Sept 15

Publication series

Name	Proceedings - IEEE International Conference on Cluster Computing, ICCC
ISSN (Print)	1552-5244

Conference

Conference	2016 IEEE International Conference on Cluster Computing, CLUSTER 2016
Country/Territory	Taiwan, Province of China
City	Taipei
Period	16/9/13 → 16/9/15

Bibliographical note

Funding Information:
This work was supported by the Institute for Information & communications Technology Promotion (IITP) grant (No. R0190-15-2012) and National Research Foundation of Korea (NRF) grant (No. 2015R1C1A1A0152105), and partially by the Ajou University research fund.

Publisher Copyright:
© 2016 IEEE.

ASJC Scopus subject areas

Software
Hardware and Architecture
Signal Processing

Access to Document

10.1109/CLUSTER.2016.81

Cite this

Mativenga, R., Paik, J. Y., Lee, J., Chung, T. S., & Kim, Y. (2016). Minimizing CMT miss penalty in selective page-level address mapping table. In Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016 (pp. 152-153). Article 7776497 (Proceedings - IEEE International Conference on Cluster Computing, ICCC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CLUSTER.2016.81

Minimizing CMT miss penalty in selective page-level address mapping table. / Mativenga, Ronnie; Paik, Joon Young; Lee, Junghee et al.
Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 152-153 7776497 (Proceedings - IEEE International Conference on Cluster Computing, ICCC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Mativenga, R, Paik, JY, Lee, J, Chung, TS & Kim, Y 2016, Minimizing CMT miss penalty in selective page-level address mapping table. in Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016., 7776497, Proceedings - IEEE International Conference on Cluster Computing, ICCC, Institute of Electrical and Electronics Engineers Inc., pp. 152-153, 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016, Taipei, Taiwan, Province of China, 16/9/13. https://doi.org/10.1109/CLUSTER.2016.81

Mativenga R, Paik JY, Lee J, Chung TS, Kim Y. Minimizing CMT miss penalty in selective page-level address mapping table. In Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 152-153. 7776497. (Proceedings - IEEE International Conference on Cluster Computing, ICCC). doi: 10.1109/CLUSTER.2016.81

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title = "Minimizing CMT miss penalty in selective page-level address mapping table",

abstract = "Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.",

author = "Ronnie Mativenga and Paik, {Joon Young} and Junghee Lee and Chung, {Tae Sun} and Youngjae Kim",

note = "Funding Information: This work was supported by the Institute for Information & communications Technology Promotion (IITP) grant (No. R0190-15-2012) and National Research Foundation of Korea (NRF) grant (No. 2015R1C1A1A0152105), and partially by the Ajou University research fund. Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016 ; Conference date: 13-09-2016 Through 15-09-2016",

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doi = "10.1109/CLUSTER.2016.81",

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N1 - Funding Information: This work was supported by the Institute for Information & communications Technology Promotion (IITP) grant (No. R0190-15-2012) and National Research Foundation of Korea (NRF) grant (No. 2015R1C1A1A0152105), and partially by the Ajou University research fund. Publisher Copyright: © 2016 IEEE.

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N2 - Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.

AB - Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.

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Minimizing CMT miss penalty in selective page-level address mapping table

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