Abstract
Directory-based cache coherence schemes are commonly used in large-scale shared-memory multiprocessors, but most of them rely on heuristics to avoid large hardware requirements. We proposed using physical address mapping on directories to significantly reduce directory size needed. This approach allows the size of directory to grow as O(cn log2 n) as in optimal pointer-based directory schemes [11], where n is the number of nodes in the system and c is the number of cache lines in each cache memory. Performance aspects of the proposed scheme are studied in detail using simulation.
Original language | English |
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Pages (from-to) | 2533-2542 |
Number of pages | 10 |
Journal | IEICE Transactions on Information and Systems |
Volume | E88-D |
Issue number | 11 |
DOIs | |
Publication status | Published - 2005 Nov |
Keywords
- Cache coherence
- Directory protocol
- Multiprocessor
- Shared memory architecture
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Vision and Pattern Recognition
- Electrical and Electronic Engineering
- Artificial Intelligence