Abstract
In convolutional neural networks (CNNs), convolutional layers consume dominant portion of computation energy due to large amount of multiply-accumulate operations (MACs). However, those MACs become meaningless (zeroes) after rectified linear unit when the convolution results become negative. In this paper, we present an efficient approach to predict and skip the convolutions generating zero outputs. The proposed two-step zero prediction approach, called mosaic CNN, can be effectively used for trading off classification accuracy for computation energy in CNN. In the mosaic CNN, the outputs of each convolutional layer are computed considering their spatial surroundings in an output feature map. Here, the types of spatial surroundings (mosaic types) can be selected to save computation energy at the expense of accuracy. In order to further save the computations, we also propose a most significant bits (MSBs) only computation scheme, where a constant value representing least significant bits compensates the MSBs only computations. The CNN accelerator supporting the combined two approaches has been implemented using the 65-nm CMOS process. The numerical results show that compared with the state-of-art processor, the proposed reconfigurable accelerator can achieve energy savings ranging from 16.99% to 29.64% for VGG-16 without seriously compromising the classification accuracy.
Original language | English |
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Article number | 8434203 |
Pages (from-to) | 770-781 |
Number of pages | 12 |
Journal | IEEE Journal on Emerging and Selected Topics in Circuits and Systems |
Volume | 8 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2018 Dec |
Bibliographical note
Funding Information:Manuscript received January 7, 2018; revised May 14, 2018; accepted July 12, 2018. Date of publication August 13, 2018; date of current version December 11, 2018. This work was supported in part by the National Research Foundation of Korea under Grant NRF-2016R1A2B4015329, in part by the Ministry of Science and ICT (MSIT), Korea, through the Information Technology Research Center (ITRC) support program supervised by the Institute for Information & communications Technology Promotion (IITP) under Grant IITP-2018-0-01433, and in part by the Industrial Strategic Technology Development Program (Development of SoC technology based on Spiking Neural Cell for smart mobile and IoT Devices) under Grant 10077445. This paper was recommended by Guest Editor V. De. (Corresponding author: Jongsun Park.) C. Kim was with the School of Electrical Engineering, Korea University, Seoul 136-701, South Korea. He is now with the DRAM Design Team, Samsung Electronics Inc., Hwaseong 18448, South Korea (e-mail: [email protected]).
Funding Information:
This work was supported in part by the National Research Foundation of Korea under Grant NRF-2016R1A2B4015329, in part by the Ministry of Science and ICT (MSIT), Korea, through the Information Technology Research Center (ITRC) support program supervised by the Institute for Information and communications Technology Promotion (IITP) under Grant IITP-2018-0-01433, and in part by the Industrial Strategic Technology Development Program (Development of SoC technology based on Spiking Neural Cell for smart mobile and IoT Devices) under Grant 10077445.
Publisher Copyright:
© 2018 IEEE.
Keywords
- Convolutional neural networks
- Energy-efficient accelerator
ASJC Scopus subject areas
- Electrical and Electronic Engineering