Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications

M. Lee, Y. Jeon, J. C. Jung, S. M. Koo, S. Kim

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)

Abstract

Based on experimental and simulation studies to gain insight into the suppression of ambipolar conduction in two distinct tunnel field-effect transistor (TFET) devices (that is, an asymmetric source-drain doping or a properly designed gate underlap), here we report on the fabrication and electrical/mechanical characterization of a flexible complementary TFET (c-TFET) inverter on a plastic substrate using multiple silicon nanowires (SiNWs) as the channel material. The static voltage transfer characteristic of the SiNW c-TFET inverter exhibits a full output voltage swing between 0 V and V dd with a high voltage gain of ∼29 and a sharp transition of 0.28 V at V dd = 3 V. A leakage power consumption of the SiNW c-TFET inverter in the standby state is as low as 17.1 pW for V dd = 3 V. Moreover, its mechanical bendability indicates that it has good fatigue properties, providing an important step towards the realization of ultralow-power flexible logic circuits.

Original languageEnglish
Article number253506
JournalApplied Physics Letters
Volume100
Issue number25
DOIs
Publication statusPublished - 2012 Jun 18

Bibliographical note

Funding Information:
This work was supported by the Future-based Technology Development Program (Nano Fields) through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0019197), World Class University (WCU, R32-2008-000-10082-0), KSSRC program [Development of printable integrated circuits based on inorganic semiconductor nanowires], National Research Foundation of Korea Grant funded by the Korean Government (2011-0003298), and the Research Grant of Kwangwoon University in 2010.

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

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