Abstract
A novel architecture design to speed up the Viterbi algorithm is proposed. By doubling the number of states in the trellis, the serial operation of a traditional Add-Compare-Select (ACS) unit is transformed into a parallel operation, thus achieving a substantial speed increase. The use of the proposed architecture would increase the speed by 33% at the expense of a faily modest increase in area, thus removing the Viterbi detector/decoder from the worst case speed bottleneck path in most high-speed applications. A simple example is shown to illustrate the proposed algorithm in Maximum Likelihood Sequence Detector.
Original language | English |
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Pages | 1664-1668 |
Number of pages | 5 |
Publication status | Published - 2000 |
Externally published | Yes |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Global and Planetary Change