On-demand solution to minimize I-cache leakage energy with maintaining performance

Sung Woo Chung, Kevin Skadron

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)


This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the performance overheads of prior policies. The proposed policy reduces leakage energy by 92.7 percent with 0.08 performance overhead on average, whereas prior policies were either prone to severe performance overhead or failed to reduce the leakage energy as much. The key to this new on-demand policy is to use branch prediction information for the wakeup prediction. In the proposed policy, inserting an extra stage for wakeup between branch prediction and fetch, allows the branch predictor to be also used as a wakeup predictor without any additional hardware. Thus, the extra stage hides the wakeup penalty, not affecting branch prediction accuracy. Though extra pipeline stages typically add to branch misprediction penalty, in this case, the extra wakeup stage on the normal fetch path can be overlapped with misprediction recovery. With such consistently accurate wakeup prediction, all cache lines except the next expected cache line(s) are in the leakage saving mode, minimizing leakage energy. We focus on super-drowsy leakage control using reduced supply voltage, because it is well suited to the instruction cache's criticality. The proposed policy can be applied to other leakage saving circuit techniques as long as the wakeup penalty is at most one cycle.

Original languageEnglish
Pages (from-to)7-24
Number of pages18
JournalIEEE Transactions on Computers
Issue number1
Publication statusPublished - 2008 Jan

Bibliographical note

Funding Information:
This work was funded by the US National Science Foundation under Grant CCF-0429765, the US Army Research Office under Grant W911NF-04-1-0288, a grant from Intel Microprocessor Research Laboratories (MRL), an IT National Scholarship Program from the Institute of Information and Technology Assessment (IITA) and Ministry of Information and Communication (MIC), Korea, and a Korea Research Foundation Grant of the Korean Government (KRF-2006-D00452). The authors would like to thank Karthik Sankaranarayanan for his help in using SimPoint and in estimating the extra energy consumption of an additional pipeline stage. They would also like to thank Nam Sung Kim for his helpful comments on validating their simulation model. Finally, they would like to thank the anonymous reviewers for their helpful feedback. S.W. Chung is the corresponding author for this paper.


  • Cache memories
  • Energy-aware systems
  • Low-power design
  • Microprocessors

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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