On the performance limits of cryogenically operated SiGe HBTs and its relation to scaling for terahertz speeds

Jiahui Yuan, John D. Cressler, Ramkumar Krithivasan, Tushar Thrivikraman, Marwan H. Khater, David C. Ahlgren, Alvin J. Joseph, Jae Sung Rieh

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49 Citations (Scopus)


The goal of achieving terahertz (THz) transistors within the silicon material system has generated significant recent interest. In this paper, we use operating temperature as an effective way of gaining a better understanding of the performance limits of SiGe HBTs and their ultimate capabilities for achieving THz speeds. Different approaches for vertical profile scaling and reduction of parasitics are addressed, and three prototype fourth-generation SiGe HBTs are compared and evaluated down to deep cryogenic temperatures, using both dc and ac measurements. A record peak fT/fmax of 463/618 GHz was achieved at 4.5 K using 130-nm lithography (309/343 GHz at 300 K), demonstrating the feasibility of reaching half-THz fT and fmax simultaneously in a silicon-based transistor. The BVCEO of this cooled SiGe HBT was 1.6 V at 4.5 K (BVCBO = 5.6 V), yielding a record fT × BVCEO product of 750 GHz · V (510 GHz · at 300 K). These remarkable levels of transistor performance and the associated interesting device physics observed at cryogenic temperatures in these devices provide important insights into further device scaling for THz speeds at room temperature. It is predicted in a new scaling roadmap that fT/fmax} of room-temperature SiGe HBTs could potentially achieve 782/910 GHz at a BVCEO of 1.1 V at the 32-nm lithographic node.

Original languageEnglish
Pages (from-to)1007-1019
Number of pages13
JournalIEEE Transactions on Electron Devices
Issue number5
Publication statusPublished - 2009

Bibliographical note

Funding Information:
Manuscript received June 13, 2008; revised January 9, 2009. First published March 21, 2009; current version published April 22, 2009. This work was supported in part by NASA ETDP, by JPL, and by IBM. The review of this paper was arranged by Editor M. Anwar. J. Yuan, J. D. Cressler, and T. Thrivikraman are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250 USA (e-mail: cressler@ece.gatech.edu). R. Krithivasan is with Intel Corporation, Hudson, MA 01749 USA. M. H. Khater is with IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. D. C. Ahlgren is with IBM, Hopewell Junction, NY 12533 USA. A. J. Joseph is with IBM, Essex Junction, VT 05452 USA. J.-S. Rieh is with the School of Electronics Engineering, Korea University, Seoul 136-701, Korea. Digital Object Identifier 10.1109/TED.2009.2016017


  • Cryogenic temperatures
  • Device scaling
  • Heterojunction bipolar transistor (HBT)
  • Noise figure
  • Silicon-germanium (SiGe)
  • Terahertz (THz)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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