On the reliability of drowsy instruction caches

Soong Hyun Shin, Sung Woo Chung, Chu Shik Jhon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


As technology scales down, the leakage energy accounts for more portion of total energy in a cache. Applying the Dynamic Voltage Scaling(DVS) to a cache, which is called a drowsy cache, is known as one of the most efficient techniques for reducing leakage energy in a cache. However, it increases the Soft Error Rate(SER) and many researchers began to doubt the reliability of a drowsy cache. In this paper, we show that the instruction cache(I-cache) can adopt the DVS without reliability problems for several reasons. First, an I-cache always stores read-only data, rarely incurring unrecoverable errors. In the I-cache, the soft error can be recovered by re-fetching from the lower level memory. Second, the effect of soft errors on performance is negligible, because the SEE is extremely low. Additional, considerable percentage of soft errors do not harm the performance. In this paper, the evaluation results show that the drowsy I-cache rarely increases unrecoverable errors and negligibly degrades the performance.

Original languageEnglish
Title of host publicationAdvances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings
PublisherSpringer Verlag
Number of pages7
ISBN (Print)3540400567, 9783540400561
Publication statusPublished - 2006
Event11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006 - Shanghai, China
Duration: 2006 Sept 62006 Sept 8

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4186 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science


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