On the scaling limits of low-frequency noise in SiGe HBTs

J. Johansen, Z. Jin, J. D. Cressler, Y. Cui, G. Niu, Q. Liang, J. S. Rieh, G. Freeman, D. Ahlgren, A. Joseph

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Low-frequency noise (LFN) is up-converted to phase noise through the nonlinearities of transistors, placing a fundamental limit on the achievable spectral purity of communications systems. One unique merit of SiGe HBTs is that they can simultaneously provide very small broadband and 1/f noise, giving them an advantage over scaled CMOS and III-V devices for high-frequency wireless building blocks limited by phase noise (e.g., oscillators and mixers). A statistical variation in the LFN spectra of small SiGe HBTs has recently been reported [1], however, and a qualitative explanation was offered which assumes a reduction in the number of noise-generating G/R traps as the device emitter area decreases [1,2]. We present, for the first time, LFN results on SiGe HBTs with fTs of 210 GHz and 350 GHz, compare geometrical scaling-induced small-size effects in 1/f noise with previous SiGe technology generations, and use 2D simulations of 1/f noise to better understand the scaling limitations of noise in SiGe HBTs.

Original languageEnglish
Title of host publication2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages12-13
Number of pages2
ISBN (Electronic)0780381394, 9780780381391
DOIs
Publication statusPublished - 2003
Externally publishedYes
EventInternational Semiconductor Device Research Symposium, ISDRS 2003 - Washington, United States
Duration: 2003 Dec 102003 Dec 12

Publication series

Name2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings

Other

OtherInternational Semiconductor Device Research Symposium, ISDRS 2003
Country/TerritoryUnited States
CityWashington
Period03/12/1003/12/12

Bibliographical note

Funding Information:
This work was supported by a Fulbright Fellowship (J. Johansen), the Semiconductor Research Corporation, IBM, and the Georgia Electronic Design Center at Georgia Tech. The wafers were fabricated at IBM Microelectronics, Essex Junction, VT.

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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