Abstract
Verification was sought for the memory operation of a single transistor type ferroelectric random access memory (1T type FeRAM) with a circuit model for a memory cell transistor combined with a precharged capacitive decoupling sensing scheme. The wiring scheme of the IT type FeRAM array was also proposed based on the operation of the fabricated memory cell transistor. As a result, the memory operation of 1T type FeRAM was confirmed at a low current level with high sensing speed and no reference cell, and the design and verification of the full chip were achieved.
Original language | English |
---|---|
Pages (from-to) | 1397-1398 |
Number of pages | 2 |
Journal | Electronics Letters |
Volume | 40 |
Issue number | 22 |
DOIs | |
Publication status | Published - 2004 Oct 28 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering