Optimal Memory Size Formula for Moving-Average Digital Phase-Locked Loop

Choon Ki Ahn, Peng Shi, Sung Hyun You

    Research output: Contribution to journalArticlepeer-review

    7 Citations (Scopus)

    Abstract

    This letter proposes a new moving-Average form of digital phase-locked loop (DPLL) that uses the average value of measurements on a memory horizon and the correction term to estimate phase information. This ensures the desired unbiasedness property for the phase information. A new formula for the optimal memory size of the proposed DPLL with minimization of the expected squared phase error is established. A numerical example is given to show that the developed DPLL has superior robustness against quantization and incorrect noise compared to the existing DPLLs.

    Original languageEnglish
    Article number7726021
    Pages (from-to)1844-1847
    Number of pages4
    JournalIEEE Signal Processing Letters
    Volume23
    Issue number12
    DOIs
    Publication statusPublished - 2016 Dec

    Bibliographical note

    Publisher Copyright:
    © 1994-2012 IEEE.

    Keywords

    • Digital phase-locked loop (DPLL)
    • moving average
    • optimal memory size
    • robustness
    • unbiasedness

    ASJC Scopus subject areas

    • Signal Processing
    • Electrical and Electronic Engineering
    • Applied Mathematics

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