Abstract
This letter proposes a new moving-Average form of digital phase-locked loop (DPLL) that uses the average value of measurements on a memory horizon and the correction term to estimate phase information. This ensures the desired unbiasedness property for the phase information. A new formula for the optimal memory size of the proposed DPLL with minimization of the expected squared phase error is established. A numerical example is given to show that the developed DPLL has superior robustness against quantization and incorrect noise compared to the existing DPLLs.
Original language | English |
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Article number | 7726021 |
Pages (from-to) | 1844-1847 |
Number of pages | 4 |
Journal | IEEE Signal Processing Letters |
Volume | 23 |
Issue number | 12 |
DOIs | |
Publication status | Published - 2016 Dec |
Keywords
- Digital phase-locked loop (DPLL)
- moving average
- optimal memory size
- robustness
- unbiasedness
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering
- Applied Mathematics