TY - JOUR
T1 - P-DRAMSim2
T2 - Exploiting thread-level parallelism in DRAMSim2
AU - Han, Miseon
AU - Kim, Seon Wook
AU - Kim, Minseong
AU - Han, Youngsun
N1 - Funding Information:
This work was partly supported by the IT R&D program of MOTIE/KEIT [10052653, Development of processing in memory architecture and parallel processing for data bounding applications] and SK hynix Inc.
Publisher Copyright:
© IEICE 2017.
PY - 2017
Y1 - 2017
N2 - Recently, with the increasing popularity of data-centric applications, the demand for greater data storage capacities is also growing rapidly. Due to the increased memory footprints, memory system simulators are confronted with serious limitations in exploring memory system behaviors and performances, as the simulation takes enormous time compared to execution in real systems. Furthermore, since emerging memory technologies such as PCM and STT-RAM are designed to execute additional algorithms for enhancing wear-leveling, reducing bit flips, etc., the limitations become worse. To resolve these problems, we propose P-DRAMSim2 that accelerates the most popularly used DRAMSim2, a state-of-the-art memory simulator, by exploiting thread-level parallelism. From our experiment, we obtained up to 15.4× and 15.7× of speedups when simulating DRAM and PCM systems, respectively, with 16 command threads compared to serial execution without any loss of accuracy.
AB - Recently, with the increasing popularity of data-centric applications, the demand for greater data storage capacities is also growing rapidly. Due to the increased memory footprints, memory system simulators are confronted with serious limitations in exploring memory system behaviors and performances, as the simulation takes enormous time compared to execution in real systems. Furthermore, since emerging memory technologies such as PCM and STT-RAM are designed to execute additional algorithms for enhancing wear-leveling, reducing bit flips, etc., the limitations become worse. To resolve these problems, we propose P-DRAMSim2 that accelerates the most popularly used DRAMSim2, a state-of-the-art memory simulator, by exploiting thread-level parallelism. From our experiment, we obtained up to 15.4× and 15.7× of speedups when simulating DRAM and PCM systems, respectively, with 16 command threads compared to serial execution without any loss of accuracy.
KW - DRAMSim2
KW - Memory system simulator
KW - Parallelization
UR - http://www.scopus.com/inward/record.url?scp=85027167632&partnerID=8YFLogxK
U2 - 10.1587/elex.14.20170591
DO - 10.1587/elex.14.20170591
M3 - Article
AN - SCOPUS:85027167632
SN - 1349-2543
VL - 14
JO - ieice electronics express
JF - ieice electronics express
IS - 15
M1 - 20170591
ER -