P-DRAMSim2: Exploiting thread-level parallelism in DRAMSim2

Miseon Han; Seon Wook Kim; Minseong Kim; Youngsun Han

doi:10.1587/elex.14.20170591

P-DRAMSim2: Exploiting thread-level parallelism in DRAMSim2

Miseon Han, Seon Wook Kim, Minseong Kim, Youngsun Han

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Recently, with the increasing popularity of data-centric applications, the demand for greater data storage capacities is also growing rapidly. Due to the increased memory footprints, memory system simulators are confronted with serious limitations in exploring memory system behaviors and performances, as the simulation takes enormous time compared to execution in real systems. Furthermore, since emerging memory technologies such as PCM and STT-RAM are designed to execute additional algorithms for enhancing wear-leveling, reducing bit flips, etc., the limitations become worse. To resolve these problems, we propose P-DRAMSim2 that accelerates the most popularly used DRAMSim2, a state-of-the-art memory simulator, by exploiting thread-level parallelism. From our experiment, we obtained up to 15.4× and 15.7× of speedups when simulating DRAM and PCM systems, respectively, with 16 command threads compared to serial execution without any loss of accuracy.

Original language	English
Article number	20170591
Journal	ieice electronics express
Volume	14
Issue number	15
DOIs	https://doi.org/10.1587/elex.14.20170591
Publication status	Published - 2017

Bibliographical note

Funding Information:
This work was partly supported by the IT R&D program of MOTIE/KEIT [10052653, Development of processing in memory architecture and parallel processing for data bounding applications] and SK hynix Inc.

Publisher Copyright:
© IEICE 2017.

Keywords

DRAMSim2
Memory system simulator
Parallelization

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1587/elex.14.20170591

Cite this

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title = "P-DRAMSim2: Exploiting thread-level parallelism in DRAMSim2",

abstract = "Recently, with the increasing popularity of data-centric applications, the demand for greater data storage capacities is also growing rapidly. Due to the increased memory footprints, memory system simulators are confronted with serious limitations in exploring memory system behaviors and performances, as the simulation takes enormous time compared to execution in real systems. Furthermore, since emerging memory technologies such as PCM and STT-RAM are designed to execute additional algorithms for enhancing wear-leveling, reducing bit flips, etc., the limitations become worse. To resolve these problems, we propose P-DRAMSim2 that accelerates the most popularly used DRAMSim2, a state-of-the-art memory simulator, by exploiting thread-level parallelism. From our experiment, we obtained up to 15.4× and 15.7× of speedups when simulating DRAM and PCM systems, respectively, with 16 command threads compared to serial execution without any loss of accuracy.",

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AU - Kim, Minseong

AU - Han, Youngsun

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Y1 - 2017

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AB - Recently, with the increasing popularity of data-centric applications, the demand for greater data storage capacities is also growing rapidly. Due to the increased memory footprints, memory system simulators are confronted with serious limitations in exploring memory system behaviors and performances, as the simulation takes enormous time compared to execution in real systems. Furthermore, since emerging memory technologies such as PCM and STT-RAM are designed to execute additional algorithms for enhancing wear-leveling, reducing bit flips, etc., the limitations become worse. To resolve these problems, we propose P-DRAMSim2 that accelerates the most popularly used DRAMSim2, a state-of-the-art memory simulator, by exploiting thread-level parallelism. From our experiment, we obtained up to 15.4× and 15.7× of speedups when simulating DRAM and PCM systems, respectively, with 16 command threads compared to serial execution without any loss of accuracy.

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P-DRAMSim2: Exploiting thread-level parallelism in DRAMSim2

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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