Recently, with the increasing popularity of data-centric applications, the demand for greater data storage capacities is also growing rapidly. Due to the increased memory footprints, memory system simulators are confronted with serious limitations in exploring memory system behaviors and performances, as the simulation takes enormous time compared to execution in real systems. Furthermore, since emerging memory technologies such as PCM and STT-RAM are designed to execute additional algorithms for enhancing wear-leveling, reducing bit flips, etc., the limitations become worse. To resolve these problems, we propose P-DRAMSim2 that accelerates the most popularly used DRAMSim2, a state-of-the-art memory simulator, by exploiting thread-level parallelism. From our experiment, we obtained up to 15.4× and 15.7× of speedups when simulating DRAM and PCM systems, respectively, with 16 command threads compared to serial execution without any loss of accuracy.
Bibliographical noteFunding Information:
This work was partly supported by the IT R&D program of MOTIE/KEIT [10052653, Development of processing in memory architecture and parallel processing for data bounding applications] and SK hynix Inc.
© IEICE 2017.
- Memory system simulator
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering