PCB layout optimization using external LDO for low EMI

Seung Hee Ryu; Seung Baek Park; Soo-Won Kim

doi:10.1109/ICCE.2015.7066548

PCB layout optimization using external LDO for low EMI

Seung Hee Ryu, Seung Baek Park, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

LDOs are useful since LDOs do not generate switching noise, while synchronous DC-DC buck converters do. Because of this advantage, it is easy for designers to ignore the importance of the system-level PCB layout design. To control EMI at the output terminal of an LDO, the proper PCB layout is essential. This paper evaluates two types of power trace layouts for LDO test benches with a 10-layer stack-up PCB. Time-domain measurement of voltage at the output terminal of an LDO and an acoustic measurement were performed for the evaluation. The voltage drop decreased by 65 mV after the layout of the linear regulator output was revised.

Original language	English
Title of host publication	2015 IEEE International Conference on Consumer Electronics, ICCE 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	610-611
Number of pages	2
ISBN (Print)	9781479975426
DOIs	https://doi.org/10.1109/ICCE.2015.7066548
Publication status	Published - 2015 Mar 23
Event	2015 IEEE International Conference on Consumer Electronics, ICCE 2015 - Las Vegas, United States Duration: 2015 Jan 9 → 2015 Jan 12

Other

Other	2015 IEEE International Conference on Consumer Electronics, ICCE 2015
Country/Territory	United States
City	Las Vegas
Period	15/1/9 → 15/1/12

Keywords

EMI reduction
LDO
System-level PCB layout

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering
Industrial and Manufacturing Engineering

Access to Document

10.1109/ICCE.2015.7066548

Cite this

Ryu, SH, Park, SB & Kim, S-W 2015, PCB layout optimization using external LDO for low EMI. in 2015 IEEE International Conference on Consumer Electronics, ICCE 2015., 7066548, Institute of Electrical and Electronics Engineers Inc., pp. 610-611, 2015 IEEE International Conference on Consumer Electronics, ICCE 2015, Las Vegas, United States, 15/1/9. https://doi.org/10.1109/ICCE.2015.7066548

@inproceedings{4cb596c0a46946b39d0ee3003f1eaf62,

title = "PCB layout optimization using external LDO for low EMI",

abstract = "LDOs are useful since LDOs do not generate switching noise, while synchronous DC-DC buck converters do. Because of this advantage, it is easy for designers to ignore the importance of the system-level PCB layout design. To control EMI at the output terminal of an LDO, the proper PCB layout is essential. This paper evaluates two types of power trace layouts for LDO test benches with a 10-layer stack-up PCB. Time-domain measurement of voltage at the output terminal of an LDO and an acoustic measurement were performed for the evaluation. The voltage drop decreased by 65 mV after the layout of the linear regulator output was revised.",

keywords = "EMI reduction, LDO, System-level PCB layout",

author = "Ryu, {Seung Hee} and Park, {Seung Baek} and Soo-Won Kim",

year = "2015",

month = mar,

day = "23",

doi = "10.1109/ICCE.2015.7066548",

language = "English",

isbn = "9781479975426",

pages = "610--611",

booktitle = "2015 IEEE International Conference on Consumer Electronics, ICCE 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2015 IEEE International Conference on Consumer Electronics, ICCE 2015 ; Conference date: 09-01-2015 Through 12-01-2015",

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AU - Ryu, Seung Hee

AU - Park, Seung Baek

AU - Kim, Soo-Won

PY - 2015/3/23

Y1 - 2015/3/23

N2 - LDOs are useful since LDOs do not generate switching noise, while synchronous DC-DC buck converters do. Because of this advantage, it is easy for designers to ignore the importance of the system-level PCB layout design. To control EMI at the output terminal of an LDO, the proper PCB layout is essential. This paper evaluates two types of power trace layouts for LDO test benches with a 10-layer stack-up PCB. Time-domain measurement of voltage at the output terminal of an LDO and an acoustic measurement were performed for the evaluation. The voltage drop decreased by 65 mV after the layout of the linear regulator output was revised.

AB - LDOs are useful since LDOs do not generate switching noise, while synchronous DC-DC buck converters do. Because of this advantage, it is easy for designers to ignore the importance of the system-level PCB layout design. To control EMI at the output terminal of an LDO, the proper PCB layout is essential. This paper evaluates two types of power trace layouts for LDO test benches with a 10-layer stack-up PCB. Time-domain measurement of voltage at the output terminal of an LDO and an acoustic measurement were performed for the evaluation. The voltage drop decreased by 65 mV after the layout of the linear regulator output was revised.

KW - EMI reduction

KW - LDO

KW - System-level PCB layout

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DO - 10.1109/ICCE.2015.7066548

M3 - Conference contribution

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SN - 9781479975426

SP - 610

EP - 611

BT - 2015 IEEE International Conference on Consumer Electronics, ICCE 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 IEEE International Conference on Consumer Electronics, ICCE 2015

Y2 - 9 January 2015 through 12 January 2015

ER -

PCB layout optimization using external LDO for low EMI

Abstract

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Keywords

ASJC Scopus subject areas

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