Phase change memory (PCM) is a byte-addressable type of non-volatile memory. Compared to other volatile and non-volatile memories, PCM is two to four times denser than dynamic random access memory (DRAM). It has better read latency than NAND flash memory. Even though the write endurance of PCM is 10 times better than NAND flash memory, it is still limited to 106 times per PCM cell. Decreasing and balancing the number of writes among PCM cells can solve the endurance problem and, where possible, keep PCM cells usable. Our objective is to design a PCR*-tree – a novel PCM-aware R*-tree that can store spatial data. Initially, we examine how R*-tree causes endurance problems in PCM, and then, we optimize it for PCM. Furthermore, the performance of R*-tree is very poor, especially for insertion, which needs to be solved since it will be used for in-memory databases. According to our experimental results, when the benchmark dataset is used, PCR*-tree dramatically reduced the number of write operations to PCM in average 30 times and also improve the performance in terms of processing time. These results suggest our new method outperforms existing ones for the PCM endurance problem, as well as in its performance.
Bibliographical noteFunding Information:
This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT, and Future Planning (2013-012524) for the third author (Byung-Won On) and supported by the Ministry of Trade, Industry and Energy (MOTIE, Korea) under Industrial Technology Innovation Program No. 10063130 and by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2016R1A2B4007498) for the fourth author (Gyu Sang Choi).
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- In-memory databases
- Spatial tree
ASJC Scopus subject areas
- Human-Computer Interaction
- Hardware and Architecture
- Library and Information Sciences
- Computational Theory and Mathematics