Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS with Nanosheet FET

Seung Geun Jung, Dongwon Jang, Seong Ji Min, Euyjin Park, Hyun Yong Yu

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)


For the first time, by using 3-D TCAD, the advantage of using complementary FET (CFET), which has vertically stacked nanosheet nFET and pFET with shared gate, is compared to standard CMOS with nanosheet FETs in perspective of CMOS inverter performance. The comparative study on CMOS operation was performed between CFET and standard CMOS in 3-nm technology node. The results indicate that, when both devices have identical DC electrical characteristics, using CFET can increase the frequency by 2.3% in iso-power and decrease power by 7.3% in iso-frequency compared to the standard CMOS with separate n/pFETs while effectively reducing the area by 55%. It is also investigated that such results are due to the approximately 4.5% low effective capacitance (Ceff) of the CFET compared to the standard CMOS. This low Ceff of CFET arises from the stacked structure, which causes the gate-fringe electric field overlap and short via pitch between nFET and pFET. Furthermore, the performance of CFET by different n/pFET separation distances, channel lengths, and widths are analyzed. This study can provide critical insight into the performance improvement by using CFET for sub 3-nm technology.

Original languageEnglish
Pages (from-to)78-82
Number of pages5
JournalIEEE Journal of the Electron Devices Society
Publication statusPublished - 2022

Bibliographical note

Publisher Copyright:
© 2013 IEEE.


  • 3-nm technology node
  • CMOS inverter
  • Complementary FET (CFET)
  • Nanosheet FET (NSHFET)
  • Technology computer-aided design(TCAD)

ASJC Scopus subject areas

  • Biotechnology
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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