TY - GEN
T1 - Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay
AU - Gong, Young Ho
AU - Jang, Hyung Beom
AU - Chung, Sung Woo
PY - 2013
Y1 - 2013
N2 - Most modern microprocessors have multi-level on-chip caches with multi-megabyte shared last-level cache (LLC). By using multi-level cache hierarchy, the whole size of on-chip caches becomes larger. The increased cache size causes the leakage power and area of the on-chip caches to increase. Recently, to reduce the leakage power and area of the SRAM based cache, the SRAM-eDRAM hybrid cache was proposed. For SRAM-eDRAM hybrid caches, however, there has not been any study to analyze the effects of the reduced area on wire delay, cache access time, and performance. By replacing half (or three fourth) of SRAM cells by small eDRAM cells for the SRAM-eDRAM hybrid caches, wire length is shortened, which eventually results in the reduction of wire delay and cache access time. In this paper, we evaluate the SRAM-eDRAM hybrid caches in terms of the energy, area, wire delay, access time, and performance. We show that the SRAM-eDRAM hybrid cache reduces the energy consumption, area, wire delay, and SRAM array access time by up to 53.9%, 49.9%, 50.4%, and 38.7%, respectively, compared to the SRAM based cache.
AB - Most modern microprocessors have multi-level on-chip caches with multi-megabyte shared last-level cache (LLC). By using multi-level cache hierarchy, the whole size of on-chip caches becomes larger. The increased cache size causes the leakage power and area of the on-chip caches to increase. Recently, to reduce the leakage power and area of the SRAM based cache, the SRAM-eDRAM hybrid cache was proposed. For SRAM-eDRAM hybrid caches, however, there has not been any study to analyze the effects of the reduced area on wire delay, cache access time, and performance. By replacing half (or three fourth) of SRAM cells by small eDRAM cells for the SRAM-eDRAM hybrid caches, wire length is shortened, which eventually results in the reduction of wire delay and cache access time. In this paper, we evaluate the SRAM-eDRAM hybrid caches in terms of the energy, area, wire delay, access time, and performance. We show that the SRAM-eDRAM hybrid cache reduces the energy consumption, area, wire delay, and SRAM array access time by up to 53.9%, 49.9%, 50.4%, and 38.7%, respectively, compared to the SRAM based cache.
KW - SRAM-eDRAM hybrid cache
KW - access time
KW - wire delay
UR - http://www.scopus.com/inward/record.url?scp=84879594007&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2013.6523661
DO - 10.1109/ISQED.2013.6523661
M3 - Conference contribution
AN - SCOPUS:84879594007
SN - 9781467349536
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 524
EP - 530
BT - Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013
T2 - 14th International Symposium on Quality Electronic Design, ISQED 2013
Y2 - 4 March 2013 through 6 March 2013
ER -