TY - GEN
T1 - Performance evaluation of a NAT subsystem on programmable network processors
AU - Park, Woojin
AU - Woo, Sinam
AU - Kim, Wook
AU - An, Sunshin
PY - 2006
Y1 - 2006
N2 - It is a challenge to prototype network applications such as NAT that needs compute-intensive packet header processing while keeping the line speed on programmable network processors. In this paper, we design, implement, and evaluate a NAT subsystem capable of run-time adaptation on an experimental board containing a pair of Intel IXP2400 network processors, which operates in switch-over mode (NAT or NAPT) based on the fullness of the available global addresses or user configuration. We evaluate and validate our system through simulations and hardware experiments. It is found that the bottleneck of the system is due to the DRAM access latency. Also, we demonstrate that our NAT subsystem can support more than five hundreds of thousands of concurrent TCP/UDP sessions and sustain the full line rate on two Gigabit Ethernet links. Our experimental results and architecture can contribute to the other designs and implementations of network services over programmable network processors since they have similar architectures, functionalities and components1.
AB - It is a challenge to prototype network applications such as NAT that needs compute-intensive packet header processing while keeping the line speed on programmable network processors. In this paper, we design, implement, and evaluate a NAT subsystem capable of run-time adaptation on an experimental board containing a pair of Intel IXP2400 network processors, which operates in switch-over mode (NAT or NAPT) based on the fullness of the available global addresses or user configuration. We evaluate and validate our system through simulations and hardware experiments. It is found that the bottleneck of the system is due to the DRAM access latency. Also, we demonstrate that our NAT subsystem can support more than five hundreds of thousands of concurrent TCP/UDP sessions and sustain the full line rate on two Gigabit Ethernet links. Our experimental results and architecture can contribute to the other designs and implementations of network services over programmable network processors since they have similar architectures, functionalities and components1.
KW - IXP2400
KW - Network address and port translation
KW - Network address translation
KW - Network processor
UR - http://www.scopus.com/inward/record.url?scp=34547240875&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:34547240875
SN - 1424402166
SN - 9781424402168
T3 - Proceedings of the International Symposium on Consumer Electronics, ISCE
SP - 282
EP - 287
BT - 2006 IEEE Tenth International Symposium on Consumer Electronics, ISCE 2006 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2006 IEEE 10th International Symposium on Consumer Electronics, ISCE 2006
Y2 - 28 June 2006 through 1 July 2006
ER -