Performance Improvement in DRAM Cell Using Novel Nitride/Metal Spacers Structure

In this paper, a novel structure of DRAM (Dynamic Random Access Memory) cell transistor which has new spacer structure of nitride/metal is investigated using 3-D technology computer-aided design simulation. When the nitride/metal spacer structure is used in a DRAM cell, the retention time increases by ~242.2 % compared conventional device structure, owing to restrain of gate-induced drain leakage which is caused by low metal work function of metal at spacer. Furthermore, the write time decreases by ~6.3 % compared conventional device structure thanks to the charge plasma effect which can virtually increase source/drain doping concentrations. It is also demonstrated that improvements in both retention time and write time are achievable within the ranges of material parameters used in current fabrication processes. Therefore, the nitride/metal spacer presents a promising technique for DRAM cells, particularly for applications in the sub-1y-nm technology node.