TY - GEN
T1 - Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array
AU - Kang, Minseok
AU - Park, Jongsun
N1 - Funding Information:
This work was supported in part by the MSIT(Ministry of Science and ICT), Korea, under the ITRC(Information Technology Research Center) support program(IITP-2021-2018-0-01433) supervised by the IITP(Institute for Information & communications Technology Promotion), and in part by the Industrial Strategic Technology Development Program(10077445, Development of SoC technology based on Spiking Neural Cell for smart mobile and IoT Devices) funded By the Ministry of Trade, Industry & Energy(MOTIE, Korea).
Publisher Copyright:
© 2021 IEEE.
PY - 2021/6/27
Y1 - 2021/6/27
N2 - Emerging device-based crossbar-array can improve energy efficiency and performance in Spiking Neural Network (SNN) that performs numerous addition and multiplication operations. However, for the large size of crossbar array, delay for SL voltage development increases due to large capacitances of bit-line, and area overhead of peripheral circuit increases significantly. In this paper, we propose STT-MRAM architecture for SNN by minimizing area overhead and operation delay with peripheral circuit optimization. When the proposed method is applied, in 512×512 crossbar array, voltage development delay is reduced by 5.75 (ns), making it possible to perform faster inference operation.
AB - Emerging device-based crossbar-array can improve energy efficiency and performance in Spiking Neural Network (SNN) that performs numerous addition and multiplication operations. However, for the large size of crossbar array, delay for SL voltage development increases due to large capacitances of bit-line, and area overhead of peripheral circuit increases significantly. In this paper, we propose STT-MRAM architecture for SNN by minimizing area overhead and operation delay with peripheral circuit optimization. When the proposed method is applied, in 512×512 crossbar array, voltage development delay is reduced by 5.75 (ns), making it possible to perform faster inference operation.
KW - STT-MRAM
KW - Sourced line (SL) voltage developing delay
KW - Spiking Neural Network (SNN)
KW - pre-charge circuit
UR - http://www.scopus.com/inward/record.url?scp=85113917889&partnerID=8YFLogxK
U2 - 10.1109/ITC-CSCC52171.2021.9501462
DO - 10.1109/ITC-CSCC52171.2021.9501462
M3 - Conference contribution
AN - SCOPUS:85113917889
T3 - 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
BT - 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
Y2 - 27 June 2021 through 30 June 2021
ER -
