Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array

Minseok Kang; Jongsun Park

doi:10.1109/ITC-CSCC52171.2021.9501462

Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array

Minseok Kang, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Emerging device-based crossbar-array can improve energy efficiency and performance in Spiking Neural Network (SNN) that performs numerous addition and multiplication operations. However, for the large size of crossbar array, delay for SL voltage development increases due to large capacitances of bit-line, and area overhead of peripheral circuit increases significantly. In this paper, we propose STT-MRAM architecture for SNN by minimizing area overhead and operation delay with peripheral circuit optimization. When the proposed method is applied, in 512×512 crossbar array, voltage development delay is reduced by 5.75 (ns), making it possible to perform faster inference operation.

Original language	English
Title of host publication	2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665435536
DOIs	https://doi.org/10.1109/ITC-CSCC52171.2021.9501462
Publication status	Published - 2021 Jun 27
Event	36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 - Jeju, Korea, Republic of Duration: 2021 Jun 27 → 2021 Jun 30

Publication series

Name	2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021

Conference

Conference	36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
Country/Territory	Korea, Republic of
City	Jeju
Period	21/6/27 → 21/6/30

Bibliographical note

Funding Information:
This work was supported in part by the MSIT(Ministry of Science and ICT), Korea, under the ITRC(Information Technology Research Center) support program(IITP-2021-2018-0-01433) supervised by the IITP(Institute for Information & communications Technology Promotion), and in part by the Industrial Strategic Technology Development Program(10077445, Development of SoC technology based on Spiking Neural Cell for smart mobile and IoT Devices) funded By the Ministry of Trade, Industry & Energy(MOTIE, Korea).

Publisher Copyright:
© 2021 IEEE.

Keywords

STT-MRAM
Sourced line (SL) voltage developing delay
Spiking Neural Network (SNN)
pre-charge circuit

ASJC Scopus subject areas

Artificial Intelligence
Computer Networks and Communications
Hardware and Architecture
Information Systems
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ITC-CSCC52171.2021.9501462

Cite this

Kang, M., & Park, J. (2021). Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array. In 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 Article 9501462 (2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-CSCC52171.2021.9501462

Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array. / Kang, Minseok; Park, Jongsun.
2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9501462 (2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kang, M & Park, J 2021, Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array. in 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021., 9501462, 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021, Institute of Electrical and Electronics Engineers Inc., 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021, Jeju, Korea, Republic of, 21/6/27. https://doi.org/10.1109/ITC-CSCC52171.2021.9501462

Kang M, Park J. Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array. In 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9501462. (2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021). doi: 10.1109/ITC-CSCC52171.2021.9501462

Kang, Minseok ; Park, Jongsun. / Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array. 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021).

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Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

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Cite this