Phase-locked loops using digital calibration technique with counter

Chan Hui Jeong; Ammar Abdullah; Kwan Joo Lee; Hoon Ki Kim; Soo Won Kim

doi:10.5370/KIEE.2011.60.2.320

Phase-locked loops using digital calibration technique with counter

Chan Hui Jeong, Ammar Abdullah, Kwan Joo Lee, Hoon Ki Kim, Soo Won Kim

Research output: Contribution to journal › Article › peer-review

Abstract

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5μA current mismatch in CP. It was designed in a standard 0.13μm CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38mW with 1.5V power supply and effective area is 0.1804mm².

Original language	English
Pages (from-to)	320-324
Number of pages	5
Journal	Transactions of the Korean Institute of Electrical Engineers
Volume	60
Issue number	2
DOIs	https://doi.org/10.5370/KIEE.2011.60.2.320
Publication status	Published - 2011 Feb

Keywords

Charge pump phase-locked loop(CPPLL)
Charge pump(CP) mismatch
Digital calibration

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.5370/KIEE.2011.60.2.320

Cite this

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title = "Phase-locked loops using digital calibration technique with counter",

abstract = "A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5μA current mismatch in CP. It was designed in a standard 0.13μm CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38mW with 1.5V power supply and effective area is 0.1804mm2.",

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AU - Jeong, Chan Hui

AU - Abdullah, Ammar

AU - Lee, Kwan Joo

AU - Kim, Hoon Ki

AU - Kim, Soo Won

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AB - A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5μA current mismatch in CP. It was designed in a standard 0.13μm CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38mW with 1.5V power supply and effective area is 0.1804mm2.

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Phase-locked loops using digital calibration technique with counter

Abstract

Keywords

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