Pipelined CPU design with FPGA in teaching computer architecture

Jong Hyuk Lee; Seung Eun Lee; Heon Chang Yu; Taeweon Suh

doi:10.1109/TE.2011.2175227

Pipelined CPU design with FPGA in teaching computer architecture

Jong Hyuk Lee, Seung Eun Lee, Heon Chang Yu, Taeweon Suh

Research output: Contribution to journal › Article › peer-review

33 Citations (Scopus)

Abstract

This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on time. The goal of the project is to educate students effectively via hands-on learning, rather than having them achieve a complete and flawless CPU design. This study reveals that 21 MIPS instructions are enough to achieve the purpose. With the addition in 2010 of the properly enforced scheduling and the FPGA system, many more students successfully completed the class project than was the case in 2009. A student survey and the independent samples t-test reveal the effectiveness of the methodology with the FPGA system. This work differs from previous work in that the devised project requires the implementation of a real CPU instead of utilizing simulators or just experimenting with ready-made complete CPU models.

Original language	English
Article number	6093707
Pages (from-to)	341-348
Number of pages	8
Journal	IEEE Transactions on Education
Volume	55
Issue number	3
DOIs	https://doi.org/10.1109/TE.2011.2175227
Publication status	Published - 2012

Bibliographical note

Funding Information:
Manuscript received May 17, 2011; revised September 30, 2011; accepted October 27, 2011. Date of publication November 30, 2011; date of current version July 31, 2012. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2011-0003422). J. H. Lee is with the Creative Informatics and Computing Institute, Korea University, Seoul 136-701, Korea. S. E. Lee is with the Department of Electronic and Information Engineering, Seoul National University of Science and Technology, Seoul 139-743, Korea. H. C. Yu and T. Suh are with the Department of Computer Science Education, Korea University, Seoul 136-701, Korea (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TE.2011.2175227

Keywords

Computer architecture
education
field programmable gate array (FPGA)
hands-on learning
incremental learning
pipeline
problem-based learning (PBL)

ASJC Scopus subject areas

Education
Electrical and Electronic Engineering

Access to Document

10.1109/TE.2011.2175227

Cite this

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abstract = "This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on time. The goal of the project is to educate students effectively via hands-on learning, rather than having them achieve a complete and flawless CPU design. This study reveals that 21 MIPS instructions are enough to achieve the purpose. With the addition in 2010 of the properly enforced scheduling and the FPGA system, many more students successfully completed the class project than was the case in 2009. A student survey and the independent samples t-test reveal the effectiveness of the methodology with the FPGA system. This work differs from previous work in that the devised project requires the implementation of a real CPU instead of utilizing simulators or just experimenting with ready-made complete CPU models.",

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note = "Funding Information: Manuscript received May 17, 2011; revised September 30, 2011; accepted October 27, 2011. Date of publication November 30, 2011; date of current version July 31, 2012. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2011-0003422). J. H. Lee is with the Creative Informatics and Computing Institute, Korea University, Seoul 136-701, Korea. S. E. Lee is with the Department of Electronic and Information Engineering, Seoul National University of Science and Technology, Seoul 139-743, Korea. H. C. Yu and T. Suh are with the Department of Computer Science Education, Korea University, Seoul 136-701, Korea (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TE.2011.2175227",

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Pipelined CPU design with FPGA in teaching computer architecture

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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