Pipelined VLSI architecture of the Viterbi decoder for IMT-2000

Keyphrases

• IMT-2000 100%
• Viterbi Decoder 100%
• Traceback 100%
• VLSI Architecture 100%
• Metric Selection 66%
• Latency 33%
• Architecture-centric 33%
• Pipelined Architecture 33%
• Multiplexer 33%
• Memory Controller 33%
• Detection Unit 33%
• Pipeline Stages 33%
• Arbitrary State 33%
• Overflow Monitoring 33%
• Truncation Effect 33%
• Subtraction Scheme 33%

Computer Science

• Very large-scale integration (VLSI) architecture 100%
• Pipelining 50%
• Memory Controller 50%
• Pipeline Stage 50%
• Traceback Operation 50%
• Datapath 50%
• Stage Pipeline 50%
• Arbitrary State 50%