TY - JOUR
T1 - PLL with dual PFDs for adjusting the loop bandwidth to input frequency ratio
AU - Woo, Youngshin
AU - Jang, Young Min
AU - Sung, Man Young
PY - 2003/1
Y1 - 2003/1
N2 - In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which the advantages of both PFDs can be combined. The sequential PFD has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by operating the appropriate PFD connected to the well-adjusted charge pump and regulating the ratio of loop bandwidth to input frequency during the acquisition process, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. This structure can improve the trade-off between acquisition behaviour and locked behaviour. The proposed PLL structure is designed to use 1.5 μm CMOS technology with 5 V supply voltage.
AB - In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which the advantages of both PFDs can be combined. The sequential PFD has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by operating the appropriate PFD connected to the well-adjusted charge pump and regulating the ratio of loop bandwidth to input frequency during the acquisition process, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. This structure can improve the trade-off between acquisition behaviour and locked behaviour. The proposed PLL structure is designed to use 1.5 μm CMOS technology with 5 V supply voltage.
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U2 - 10.1080/002072103100138525
DO - 10.1080/002072103100138525
M3 - Article
AN - SCOPUS:0142167585
SN - 0020-7217
VL - 90
SP - 43
EP - 55
JO - International Journal of Electronics
JF - International Journal of Electronics
IS - 1
ER -