PLL with dual PFDs for adjusting the loop bandwidth to input frequency ratio

In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which the advantages of both PFDs can be combined. The sequential PFD has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by operating the appropriate PFD connected to the well-adjusted charge pump and regulating the ratio of loop bandwidth to input frequency during the acquisition process, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. This structure can improve the trade-off between acquisition behaviour and locked behaviour. The proposed PLL structure is designed to use 1.5 μm CMOS technology with 5 V supply voltage.