Practical approach to power integrity-driven design process for power-delivery networks

Keyphrases

• Design Process 100%
• Design Basis 100%
• Power Integrity 100%
• Power Delivery System 100%
• On-chip Power 100%
• Target Impedance 100%
• On chip 50%
• Minimum Value 50%
• Practical Design 50%
• Worst-case Conditions 50%
• Measurement Results 50%
• Power Noise 50%
• Ball Grid Array 50%
• Multilayer Ceramic Capacitor 50%
• Design Strategy 50%
• Noise Problem 50%
• Combining Vectors 50%
• Current Profile 50%
• Application-specific Processors 50%
• Optimization Strategy 50%
• Chip Model 50%
• Voltage Noise 50%
• RLC Circuits 50%
• Voltage Droop 50%
• Power Integrity Analysis 50%
• Vector Network Analyzers Measurements 50%

Engineering

• Design Process 100%
• Simulation Result 50%
• Good Agreement 50%
• System-on-Chip 50%
• Network Analyzer 50%
• Noise Voltage 50%
• Noise Power 50%
• Current Profile 50%
• Ball Grid Arrays 50%