Abstract
This paper introduces a practical methodology to improve power integrity performance of the chip-package-PCB systems for smart TVs. For power integrity analysis, a chip, package and PCB are modeled as lumped element circuits for simplicity. Case studies are presented to optimize MLCC placement using chip-package-PCB co-simulation under fixed SoC design. In case studies, CPU power net of an application processor is chosen, and voltage droop is measured as a design weight on each physical domains. The introduced methodology is evaluated through experimental verifications.
Original language | English |
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Title of host publication | 2015 IEEE International Conference on Consumer Electronics, ICCE 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 594-595 |
Number of pages | 2 |
ISBN (Print) | 9781479975426 |
DOIs | |
Publication status | Published - 2015 Mar 23 |
Event | 2015 IEEE International Conference on Consumer Electronics, ICCE 2015 - Las Vegas, United States Duration: 2015 Jan 9 → 2015 Jan 12 |
Other
Other | 2015 IEEE International Conference on Consumer Electronics, ICCE 2015 |
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Country/Territory | United States |
City | Las Vegas |
Period | 15/1/9 → 15/1/12 |
Keywords
- AP
- decoupling capacitor
- ODC
- ODR
- on co-simulation
- power integrity
- power modeling
- power noise
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering
- Industrial and Manufacturing Engineering