Process algebraic model of superscalar processor programs for instruction level timing analysis

Hee Jun Yoo, Jin Young Choi

    Research output: Chapter in Book/Report/Conference proceedingChapter

    Abstract

    This paper illustrates a formal technique for describing timing properties and resource constraints of pipelined out of order superscalar processor instructions at a high level. The degree of parallelism depends on the multiplicity of hardware functional units as well as data dependencies among instructions. Thus, the timing properties of a superscalar program are difficult to analyze and predict. We describe how to model the instruction level architecture of a superscalar processor using ACSR and how to derive the temporal behavior of an assembly program using ACSR laws. Our approach is to model superscalar processor registers as ACSR resources, instructions as ACSR processes, and use ACSR priorities to achieve maximum possible instruction-level parallelism.

    Original languageEnglish
    Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    EditorsVictor Malyshkin
    PublisherSpringer Verlag
    Pages180-184
    Number of pages5
    ISBN (Print)3540406735
    DOIs
    Publication statusPublished - 2003

    Publication series

    NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    Volume2763
    ISSN (Print)0302-9743
    ISSN (Electronic)1611-3349

    ASJC Scopus subject areas

    • Theoretical Computer Science
    • General Computer Science

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