TY - GEN
T1 - Processor-based decoupled PDP timing controller design
AU - Na, Yeoul
AU - Hwang, Seok Joong
AU - Lee, Cheol Ho
AU - Min, Junkyu
AU - Kim, Taejin
AU - Kim, Seon Wook
PY - 2011
Y1 - 2011
N2 - This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.
AB - This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.
UR - http://www.scopus.com/inward/record.url?scp=79952921402&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79952921402&partnerID=8YFLogxK
U2 - 10.1109/ICCE.2011.5722909
DO - 10.1109/ICCE.2011.5722909
M3 - Conference contribution
AN - SCOPUS:79952921402
SN - 9781424487127
T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
SP - 867
EP - 868
BT - 2011 IEEE International Conference on Consumer Electronics, ICCE 2011
T2 - 2011 IEEE International Conference on Consumer Electronics, ICCE 2011
Y2 - 9 January 2011 through 12 January 2011
ER -