PVT variation tolerant current source with on-chip digital self-calibration

Moo Young Kim; Hokyu Lee; Chulwoo Kim

doi:10.1109/TVLSI.2011.2109971

PVT variation tolerant current source with on-chip digital self-calibration

Moo Young Kim, Hokyu Lee, Chulwoo Kim

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm ² and consumes 94.9 μ W at a supply voltage of 1.0 V.

Original language	English
Article number	5720543
Pages (from-to)	737-741
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	20
Issue number	4
DOIs	https://doi.org/10.1109/TVLSI.2011.2109971
Publication status	Published - 2012 Apr

Bibliographical note

Funding Information:
Manuscript received April 26, 2010; revised September 13, 2010 and December 22, 2010; accepted January 13, 2011. Date of publication February 28, 2011; date of current version March 12, 2012. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (R0A-2007-000-20059-0).

Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.

Keywords

All digital gates
current source
on-chip
process, supply voltage, and temperature (PVT) detector
self-calibration

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/TVLSI.2011.2109971

Cite this

@article{29569005c3c74da2aa8d9b5e755d01a4,

title = "PVT variation tolerant current source with on-chip digital self-calibration",

abstract = "A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm 2 and consumes 94.9 μ W at a supply voltage of 1.0 V.",

keywords = "All digital gates, current source, on-chip, process, supply voltage, and temperature (PVT) detector, self-calibration",

author = "Kim, {Moo Young} and Hokyu Lee and Chulwoo Kim",

note = "Funding Information: Manuscript received April 26, 2010; revised September 13, 2010 and December 22, 2010; accepted January 13, 2011. Date of publication February 28, 2011; date of current version March 12, 2012. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (R0A-2007-000-20059-0). Copyright: Copyright 2012 Elsevier B.V., All rights reserved.",

year = "2012",

month = apr,

doi = "10.1109/TVLSI.2011.2109971",

language = "English",

volume = "20",

pages = "737--741",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - PVT variation tolerant current source with on-chip digital self-calibration

AU - Kim, Moo Young

AU - Lee, Hokyu

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received April 26, 2010; revised September 13, 2010 and December 22, 2010; accepted January 13, 2011. Date of publication February 28, 2011; date of current version March 12, 2012. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (R0A-2007-000-20059-0). Copyright: Copyright 2012 Elsevier B.V., All rights reserved.

PY - 2012/4

Y1 - 2012/4

N2 - A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm 2 and consumes 94.9 μ W at a supply voltage of 1.0 V.

AB - A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm 2 and consumes 94.9 μ W at a supply voltage of 1.0 V.

KW - All digital gates

KW - current source

KW - on-chip

KW - process, supply voltage, and temperature (PVT) detector

KW - self-calibration

UR - http://www.scopus.com/inward/record.url?scp=84858997296&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84858997296&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2011.2109971

DO - 10.1109/TVLSI.2011.2109971

M3 - Article

AN - SCOPUS:84858997296

SN - 1063-8210

VL - 20

SP - 737

EP - 741

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 4

M1 - 5720543

ER -

PVT variation tolerant current source with on-chip digital self-calibration

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this