Radiation hardened successive-approximation ADC with error detection circuits

For several decades, radiation-hardened-by-design (RHBD) techniques have been developed to meet the design requirements of irradiating environment in nuclear power plants. Improvements on the circuit side for radiation sensors in performance, chip size, and radiation hardening ability have been adopted in current plant systems; however, next generation reactors and/or preparation for severe events in existing reactors require advanced circuit structures that can provide relatively long viability in harsh conditions. In order to maintain performances of electronics in high radiating environments, we propose to develop a small-area, low resource-overhead data-converter architecture that is immune to radiation impact events, an architecture that includes three kinds of novel radiation-hardened (rad-hard) designs for each analog and digital circuit in an ADC structure: a) error detectable tri-state buffer for flip flop against DSET, b) error detection storage in flip flop against SEU, and c) analog algorithm for the analog parts of an SAR ADC. The novel ADC architecture including the three RHBD techniques was implemented in a standard 180 nm CMOS technology with a 1.8 V supply voltage. Simulation results show that the techniques can successfully recognize errors induced by radiation impact events. The static power consumption was 123 μW with the sampling rate 36 MS/s and resolution of 8 bits. The performances could be highly advanced under fine-tune designs.