Rank order coding based spiking convolutional neural network architecture with energy-efficient membrane voltage updates

Spiking neural network (SNN) system that uses rank order coding (ROC) as input spike encoding, generally suffers from low recognition accuracy and unnecessary computations that increase complexities. In this paper, we present a Spiking convolutional neural network (Spiking CNN) architecture that significantly improves recognition accuracy as well as computation efficiencies based on a novel ROC and modified kernel sizes. The proposed ROC generates spike trains based on maximum input value without sorting operations. In addition, as the recognition accuracy is affected by the reduced number of spikes as layers become deeper, the proposed ROC is inserted just before the final layer to increase the number of input spikes. The 2 × 2 pooling kernels are also replaced with 4 × 4 to reduce the network size. The hardware architecture of the proposed Spiking CNN has been implemented using 65 nm CMOS process. Neuron-centric membrane voltage update approach is also efficiently exploited in convolutional and fully connected layers to improve the hardware energy efficiencies. The Spiking CNN processor is seamlessly processing 2.85 K classifications per second with 6.79 uJ/classification. It also achieves 90.2% of recognition accuracy for MNIST dataset using unsupervised learning with STDP.