Reliable cache memory design for sensor networks

With the advance of processor technology, critical device parameters are significantly affected by the process variation. Subsequently, these critical parameters result in high access latencies, significant leakage power and abnormal high temperature. Cache memory circuits are easily affected by the process variation than any other hardware components; due to the densely tied transistors. Moreover, the process variation decreases both the yield of the chip and the lifetime of cache memory used in resource limited devices. Cache memory used in resource limited devices may get affected easily by the process variation due to hostile environments. In this paper, we introduce a simple but very effective process variation tolerant technique using the conventional cache replacement policies. This technique selects the cache block replacement victims excluding the affected cache block by the process variation. Without additional hardware components, the proposed technique can handle the affected cache block minimizing the performance loss. Our experiments show that when we adopted our proposed idea, the performance penalty is less than 1 % in case of 12.5% cache blocks cannot be used. Under the severe process variation, our proposed idea deteriorates the performance by only about 2%. By applying our technique in cache memory of resource limited devices, sensor nodes used in sensor networks will be more reliable.