Reliable low-power digital signal processing via reduced precision redundancy

Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review

162 Citations (Scopus)


In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires a reduced precision replica whose output can be employed as the corrected output in case the original system computes erroneously. When combined with voltage overscaling (VOS), the resulting soft digital signal processing system achieves up to 60% and 44% energy savings with no loss in the signal-to-noise ratio (SNR) for receive filtering in a QPSK system and the butterfly of fast Fourier transform (FFT) in a WLAN OFDM system, respectively. These energy savings are with respect to optimally scaled (i.e., the supply voltage equals the critical voltage Vdd-cr it) present day systems. Further, we show that the RPR technique is able to maintain the output SNR for error rates of up to 0.09/sample and 0.06/sample in an finite impulse response filter and a FFT block, respectively.

Original languageEnglish
Pages (from-to)497-510
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number5
Publication statusPublished - 2004 May

Bibliographical note

Funding Information:
Manuscript received May 2, 2003; revised September 29, 2003. This research was supported in part by the Microelectronics Advanced Research Corporation (MARCO) sponsored Gigascale Silicon Research Center and National Science Foundation under Grant CCR 99-79381 and Grant CCR 00-85929.


  • Digital signal processing
  • Low-power
  • Noise-tolerance
  • Reliability
  • Supply voltage

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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