Representation Learning for Wafer Pattern Recognition in Semiconductor Manufacturing Process

The Demand for low-power and high-performance semiconductors has rapidly increased. To improve the competitiveness of system semiconductor companies, an efficient defect management process through Automatic Defect Classification (ADC) is essential. However, as semiconductor patterns are miniaturized, defects are becoming very small. It is becoming increasingly difficult for scanning electron microscope (SEM) equipment to accurately find defects. In addition, a lot of costs is required for image collection, learning, and classification to increase defect detection accuracy. In this study, we proposed a novel volumetric representation learning to perform 3D wafer handling in the Wafer Pattern Recognition (WPR) framework. The proposed method generates a 3D representation using a structure generator and pseudo-rendering and then performs appropriate pattern recognition. The experimental results demonstrate the 3D representation shows competitive performance compared to the existing model with a performance difference of 2% to 22% based on the F-score compared to the 2D image. Also, in terms of the same cost, it is expected that it will lead to better performance if we can overcome the limitations of 2D and consider the increase in cost for 3D models. Consequently, it gives feedback to the ADC, and higher productivity in semiconductor products is expected.