Retention enhancement through capacitance-dependent voltage division analysis in 3D stackable TaO_x/HfO₂-based selectorless memristor

Sneak path current generated by adjacent cells in three-dimensional (3D) memristor arrays must be curbed while securing the multi-bit storage capability of each cell to aid in the cost-effective increase in array size. For this purpose, a 3D stackable TaO_x/HfO₂-based selectorless memristor has been proposed and optimized via capacitance-dependent voltage division analysis. The proposed device utilizes the formation or rupture of conductive filaments for self-rectifying resistive switching operation, in contrast to nonfilamentary devices that often exploit the change in the charge state of the electron trap. This approach enables the reduction of the trapped charge leakage through the interface between the resistive switching and metal layers effectively, giving rise to excellent retention properties (>5 × 10⁵ s). Furthermore, the proposed device exhibits a sufficiently high on/off ratio (~1.35 × 10³), rectification ratio (~2.3 × 10³), endurance (1.5 × 10² cycles), and low resistance variation (standard deviation <0.022). Moreover, multilevel operations are facilitated, making the proposed device suitable for high-density, nonvolatile memory applications.