Revisited parameter extraction methodology for electrical characterization of junctionless transistors

D. Y. Jeon, S. J. Park, M. Mouis, M. Berthomé, S. Barraud, G. T. Kim, G. Ghibaudo

Research output: Contribution to journalArticlepeer-review

96 Citations (Scopus)


Several electrical parameters characterize device performance, electron transport and doping level in MOS transistors. In this paper, Junctionless Transistors (JLTs) fabricated on (100) silicon on insulator (SOI) wafer with 145 nm thick BOX and 9 nm silicon thickness were considered. Parameter extraction methodologies were revisited in order to account for the unique electrical properties of JLT devices. The deduced parameters, such as threshold voltage, flat-band voltage, drain induced barrier lowering (DIBL), low field mobility and channel doping level, are shown to reveal the specific features of JLT compared to conventional inversion-mode transistors.

Original languageEnglish
Pages (from-to)86-93
Number of pages8
JournalSolid-State Electronics
Publication statusPublished - 2013

Bibliographical note

Funding Information:
This work was supported by European Union 7th Framework Program project SQWIRE under Grant agreements No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Converging Research Center Program, 2012K001313 and Global Frontier Research Program, No. 2011-0031638).


  • Channel doping level
  • Drain induced barrier lowering (DIBL)
  • Flat-band voltage (V)
  • Junctionless transistors (JLTs)
  • Low field mobility (μ)
  • Threshold voltage (V)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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