TY - GEN
T1 - Runtime parallelization of legacy code on a transactional memory system
AU - DeVuyst, Matthew
AU - Tullsen, Dean M.
AU - Kim, Seon Wook
N1 - Copyright:
Copyright 2011 Elsevier B.V., All rights reserved.
PY - 2011
Y1 - 2011
N2 - This paper proposes a new runtime parallelization technique, based on a dynamic optimization framework, to automatically parallelize single-threaded legacy programs. It heavily leverages the optimistic concurrency of transactional memory. This work addresses a number of challenges posed by this type of parallelization and quantifies the trade-offs of some of the design decisions, such as how to select good loops for parallelization, how to partition the iteration space among parallel threads, how to handle loop-carried dependencies, and how to transition from serial to parallel execution and back. The simulated implementation of runtime parallelization shows a potential speedup of 1.36 for the NAS benchmarks and a 1.34 speedup for the SPEC 2000 CPU floating point benchmarks when using two cores for parallel execution.
AB - This paper proposes a new runtime parallelization technique, based on a dynamic optimization framework, to automatically parallelize single-threaded legacy programs. It heavily leverages the optimistic concurrency of transactional memory. This work addresses a number of challenges posed by this type of parallelization and quantifies the trade-offs of some of the design decisions, such as how to select good loops for parallelization, how to partition the iteration space among parallel threads, how to handle loop-carried dependencies, and how to transition from serial to parallel execution and back. The simulated implementation of runtime parallelization shows a potential speedup of 1.36 for the NAS benchmarks and a 1.34 speedup for the SPEC 2000 CPU floating point benchmarks when using two cores for parallel execution.
KW - Dynamic optimization
KW - Parallelization
KW - Transactional memory
UR - http://www.scopus.com/inward/record.url?scp=79952938772&partnerID=8YFLogxK
U2 - 10.1145/1944862.1944882
DO - 10.1145/1944862.1944882
M3 - Conference contribution
AN - SCOPUS:79952938772
SN - 9781450302418
T3 - HiPEAC'11 - Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
SP - 127
EP - 136
BT - HiPEAC'11 - Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
T2 - 6th International Conference on High Performance and Embedded Architectures and Compilers, HiPEAC'11
Y2 - 24 January 2011 through 26 January 2011
ER -