Sensitivity based error resilient techniques for energy efficient deep neural network accelerators

Wonseok Choi, Dongyeob Shin, Jongsun Park, Swaroop Ghosh

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    39 Citations (Scopus)

    Abstract

    With inherent algorithmic error resilience of deep neural networks (DNNs), supply voltage scaling could be a promising technique for energy efficient DNN accelerator design. In this paper, we propose novel error resilient techniques to enable aggressive voltage scaling by exploiting different amount of error resilience (sensitivity) with respect to DNN layers, filters, and channels. First, to rapidly evaluate filter/channel-level weight sensitivities of large scale DNNs, first-order Taylor expansion is used, which accurately approximates weight sensitivity from actual error injection simulation. With measured timing error probability of each multiply-accumulate (MAC) units considering process variations, the sensitivity variation among filter weights can be leveraged to design DNN accelerator, such that the computations with more sensitive weights are assigned to more robust MAC units, while those with less sensitive weights are assigned to less robust MAC units. Based on post-synthesis timing simulations, 51% energy savings has been achieved with CIFAR-10 dataset using VGG-9 compared to state-of-the-art timing error recovery technique with the same constraint of 3% accuracy loss.

    Original languageEnglish
    Title of host publicationProceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781450367257
    DOIs
    Publication statusPublished - 2019 Jun 2
    Event56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States
    Duration: 2019 Jun 22019 Jun 6

    Publication series

    NameProceedings - Design Automation Conference
    ISSN (Print)0738-100X

    Conference

    Conference56th Annual Design Automation Conference, DAC 2019
    Country/TerritoryUnited States
    CityLas Vegas
    Period19/6/219/6/6

    Bibliographical note

    Funding Information:
    This work was supported by the MSIT(Ministry of Science and ICT), Korea, under the ITRC(Information Technology Research Center) support program(IITP-2019-2018-0-01433) supervised by the IITP(Institute for Information & communications Technology Promotion) and the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIP) (No. NRF-2016R1A2B4015329) and the Industrial Strategic Technology Development Program(10077445, Development of SoC technology based on Spiking Neural Cell for smart mobile and IoT Devices) funded By the Ministry of Trade, Industry & Energy(MOTIE, Korea).

    Publisher Copyright:
    © 2019 Association for Computing Machinery.

    ASJC Scopus subject areas

    • Computer Science Applications
    • Control and Systems Engineering
    • Electrical and Electronic Engineering
    • Modelling and Simulation

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