Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors

Dae Young Jeon; So Jeong Park; Mireille Mouis; Sylvain Barraud; Gyu Tae Kim; Gerard Ghibaudo

doi:10.1109/EUROSOI-ULIS45800.2019.9041921

Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors

Dae Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu Tae Kim, Gerard Ghibaudo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (V_gb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (V_th) and flat-band voltage (V_fb) of JLTs. In addition, series resistance (Ra) of JLTs was dependent on V_gband back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable R_sd effects. The R_sdwas extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.

Original language	English
Title of host publication	2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728116587
DOIs	https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041921
Publication status	Published - 2019 Apr
Event	2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019 - Grenoble, France Duration: 2019 Apr 1 → 2019 Apr 3

Publication series

Name	2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019

Conference

Conference	2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019
Country/Territory	France
City	Grenoble
Period	19/4/1 → 19/4/3

Bibliographical note

Funding Information:
This work was supported in part by the European Union 7th Framework Program Project SQWIRE under Grant 257111, in part by the Korea Institute of Science and Technology (KIST) Institutional Program, in part by the National Research Foundation of Korea under Grants NRF- 2016R1A6A3A11933511, NRF-2017M3D9A1073924, and NRF-2017M3A7B4049167, and in part by the Korea University Grant.

Publisher Copyright:
© 2019 IEEE.

Keywords

back biasing effects
junctionless transistors
numerical simulation
series resistance

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/EUROSOI-ULIS45800.2019.9041921

Cite this

Jeon, D. Y., Park, S. J., Mouis, M., Barraud, S., Kim, G. T., & Ghibaudo, G. (2019). Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. In 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019 Article 9041921 (2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041921

Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. / Jeon, Dae Young; Park, So Jeong; Mouis, Mireille et al.
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9041921 (2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jeon, DY, Park, SJ, Mouis, M, Barraud, S, Kim, GT & Ghibaudo, G 2019, Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. in 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019., 9041921, 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019, Institute of Electrical and Electronics Engineers Inc., 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019, Grenoble, France, 19/4/1. https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041921

Jeon DY, Park SJ, Mouis M, Barraud S, Kim GT, Ghibaudo G. Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. In 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 9041921. (2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019). doi: 10.1109/EUROSOI-ULIS45800.2019.9041921

Jeon, Dae Young ; Park, So Jeong ; Mouis, Mireille et al. / Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019).

@inproceedings{e2c0134c512440558b554c4353982739,

title = "Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors",

abstract = "Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (Vgb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (Vth) and flat-band voltage (Vfb) of JLTs. In addition, series resistance (Ra) of JLTs was dependent on Vgband back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable Rsd effects. The Rsdwas extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.",

keywords = "back biasing effects, junctionless transistors, numerical simulation, series resistance",

author = "Jeon, {Dae Young} and Park, {So Jeong} and Mireille Mouis and Sylvain Barraud and Kim, {Gyu Tae} and Gerard Ghibaudo",

note = "Funding Information: This work was supported in part by the European Union 7th Framework Program Project SQWIRE under Grant 257111, in part by the Korea Institute of Science and Technology (KIST) Institutional Program, in part by the National Research Foundation of Korea under Grants NRF- 2016R1A6A3A11933511, NRF-2017M3D9A1073924, and NRF-2017M3A7B4049167, and in part by the Korea University Grant. Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019 ; Conference date: 01-04-2019 Through 03-04-2019",

year = "2019",

month = apr,

doi = "10.1109/EUROSOI-ULIS45800.2019.9041921",

language = "English",

series = "2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019",

}

TY - GEN

T1 - Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors

AU - Jeon, Dae Young

AU - Park, So Jeong

AU - Mouis, Mireille

AU - Barraud, Sylvain

AU - Kim, Gyu Tae

AU - Ghibaudo, Gerard

N1 - Funding Information: This work was supported in part by the European Union 7th Framework Program Project SQWIRE under Grant 257111, in part by the Korea Institute of Science and Technology (KIST) Institutional Program, in part by the National Research Foundation of Korea under Grants NRF- 2016R1A6A3A11933511, NRF-2017M3D9A1073924, and NRF-2017M3A7B4049167, and in part by the Korea University Grant. Publisher Copyright: © 2019 IEEE.

PY - 2019/4

Y1 - 2019/4

N2 - Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (Vgb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (Vth) and flat-band voltage (Vfb) of JLTs. In addition, series resistance (Ra) of JLTs was dependent on Vgband back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable Rsd effects. The Rsdwas extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.

AB - Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (Vgb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (Vth) and flat-band voltage (Vfb) of JLTs. In addition, series resistance (Ra) of JLTs was dependent on Vgband back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable Rsd effects. The Rsdwas extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.

KW - back biasing effects

KW - junctionless transistors

KW - numerical simulation

KW - series resistance

UR - http://www.scopus.com/inward/record.url?scp=85083160657&partnerID=8YFLogxK

U2 - 10.1109/EUROSOI-ULIS45800.2019.9041921

DO - 10.1109/EUROSOI-ULIS45800.2019.9041921

M3 - Conference contribution

AN - SCOPUS:85083160657

T3 - 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019

BT - 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019

Y2 - 1 April 2019 through 3 April 2019

ER -

Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors

Abstract

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