Sharded Router: A novel on-chip router architecture employing bandwidth sharding and stealing

Junghee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Jongman Kim

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


Packet-based networks-on-chip (NoC) are considered among the most viable candidates for the on-chip interconnection network of many-core chips. Unrelenting increases in the number of processing elements on a single chip die necessitate a scalable and efficient communication fabric. The resulting enlargement of the on-chip network size has been accompanied by an equivalent widening of the physical inter-router channels. However, the growing link bandwidth is not fully utilized, because the packet size is not always a multiple of the channel width. While slicing of the physical channel enhances link utilization, it incurs additional delay, because the number of flit per packet also increases. This paper proposes a novel router micro-architecture that employs fine-grained bandwidth ''sharding'' (i.e., partitioning) and stealing in order to mitigate the elevation in the zeroload latency caused by slicing. Consequently, the zero-load latency of the Sharded Router becomes identical with that of a conventional router, whereas its throughput is markedly improved by fully utilizing all available bandwidth. Detailed experiments using a full-system simulation framework indicate that the proposed router reduces the average network latency by up to 19% and the execution time of real multi-threaded workloads by up to 43%. Finally, hardware synthesis analysis verifies the modest area overhead of the Sharded Router over a conventional design.

Original languageEnglish
Pages (from-to)372-388
Number of pages17
JournalParallel Computing
Issue number9
Publication statusPublished - 2013
Externally publishedYes


  • Bandwidth slicing
  • Channel width
  • Link bit-width
  • Network-on-chip
  • Physically segregated networks

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Networks and Communications
  • Computer Graphics and Computer-Aided Design
  • Artificial Intelligence


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