Computer Science
Networks on Chips
100%
Router Architecture
100%
Sharding
100%
Many-Core
50%
Execution Time
50%
Link Utilization
50%
Systems Simulation
50%
single-chip
50%
Link Bandwidth
50%
Interconnection Networks
50%
Processing Element
50%
Network Latency
50%
Router Microarchitecture
50%
Physical Channel
50%
Load Latency
50%
Hardware Synthesis
50%
Keyphrases
Router
100%
On-chip Router
100%
Sharding
100%
Latency
33%
Network on chip
33%
Execution Time
16%
Efficient Communication
16%
Packet Switching
16%
Available Bandwidth
16%
Channel Width
16%
Enlargement
16%
Link Utilization
16%
Single chip
16%
Packet Size
16%
Physical Channel
16%
Simulation Framework
16%
Conventional Design
16%
Area Overhead
16%
Link Bandwidth
16%
Full-system Simulation
16%
Processing Element
16%
Communication Fabrics
16%
Analysis-by-synthesis
16%
Network Latency
16%
Scalable Communication
16%
Hardware Synthesis
16%
Manycore chips
16%
On-chip Interconnection Networks
16%
Router Microarchitecture
16%