Short Word-Line Pulse with Fast Bit-Line Boosting for High Throughput 6T SRAM-based Compute In-memory Design

Minseo Kim, Jongsun Park

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    In order to get over the read disturbance in SRAM-based Compute In-Memory (CIM), 6T SRAM bit-cell with underdrived Word-Line (WL) has been widely adopted. However, underdrived WL suffers from slower Bit-Line (BL) discharge, which eventually increases the CIM latency. In this paper, we propose a short WL pulse with fast BL boosting technique. Short WL pulse approach can efficiently reduce the read disturbance while BL is discharged through BL boosting circuit so that fast BL discharging time is guaranteed with little area overhead and higher reliability. 6T SRAM bit-cell array with BL boosting has been implemented in CMOS 28nm process, and the discharging time is decreased by 63.0% compared to the conventional WL underdrive technique.

    Original languageEnglish
    Title of host publicationProceedings - International SoC Design Conference 2021, ISOCC 2021
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages103-104
    Number of pages2
    ISBN (Electronic)9781665401746
    DOIs
    Publication statusPublished - 2021
    Event18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of
    Duration: 2021 Oct 62021 Oct 9

    Publication series

    NameProceedings - International SoC Design Conference 2021, ISOCC 2021

    Conference

    Conference18th International System-on-Chip Design Conference, ISOCC 2021
    Country/TerritoryKorea, Republic of
    CityJeju Island
    Period21/10/621/10/9

    Bibliographical note

    Publisher Copyright:
    © 2021 IEEE.

    Keywords

    • BL Boosting
    • Read Disturbance
    • Short WL

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Information Systems
    • Hardware and Architecture
    • Electrical and Electronic Engineering

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