In order to get over the read disturbance in SRAM-based Compute In-Memory (CIM), 6T SRAM bit-cell with underdrived Word-Line (WL) has been widely adopted. However, underdrived WL suffers from slower Bit-Line (BL) discharge, which eventually increases the CIM latency. In this paper, we propose a short WL pulse with fast BL boosting technique. Short WL pulse approach can efficiently reduce the read disturbance while BL is discharged through BL boosting circuit so that fast BL discharging time is guaranteed with little area overhead and higher reliability. 6T SRAM bit-cell array with BL boosting has been implemented in CMOS 28nm process, and the discharging time is decreased by 63.0% compared to the conventional WL underdrive technique.
|Title of host publication||Proceedings - International SoC Design Conference 2021, ISOCC 2021|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2021|
|Event||18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of|
Duration: 2021 Oct 6 → 2021 Oct 9
|Name||Proceedings - International SoC Design Conference 2021, ISOCC 2021|
|Conference||18th International System-on-Chip Design Conference, ISOCC 2021|
|Country/Territory||Korea, Republic of|
|Period||21/10/6 → 21/10/9|
Bibliographical noteFunding Information:
This work was supported by National R&D Program through the National Research Foundation of Korea funded by Ministry of Science and ICT (NRF-2020M3F3A2A01082591).
© 2021 IEEE.
- BL Boosting
- Read Disturbance
- Short WL
ASJC Scopus subject areas
- Computer Networks and Communications
- Information Systems
- Hardware and Architecture
- Electrical and Electronic Engineering