Short Word-Line Pulse with Fast Bit-Line Boosting for High Throughput 6T SRAM-based Compute In-memory Design

Minseo Kim; Jongsun Park

doi:10.1109/ISOCC53507.2021.9613869

Short Word-Line Pulse with Fast Bit-Line Boosting for High Throughput 6T SRAM-based Compute In-memory Design

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In order to get over the read disturbance in SRAM-based Compute In-Memory (CIM), 6T SRAM bit-cell with underdrived Word-Line (WL) has been widely adopted. However, underdrived WL suffers from slower Bit-Line (BL) discharge, which eventually increases the CIM latency. In this paper, we propose a short WL pulse with fast BL boosting technique. Short WL pulse approach can efficiently reduce the read disturbance while BL is discharged through BL boosting circuit so that fast BL discharging time is guaranteed with little area overhead and higher reliability. 6T SRAM bit-cell array with BL boosting has been implemented in CMOS 28nm process, and the discharging time is decreased by 63.0% compared to the conventional WL underdrive technique.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	103-104
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613869
Publication status	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/10/6 → 21/10/9

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Keywords

BL Boosting
Read Disturbance
Short WL

ASJC Scopus subject areas

Computer Networks and Communications
Information Systems
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC53507.2021.9613869

Cite this

Kim, M., & Park, J. (2021). Short Word-Line Pulse with Fast Bit-Line Boosting for High Throughput 6T SRAM-based Compute In-memory Design. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 103-104). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613869

Short Word-Line Pulse with Fast Bit-Line Boosting for High Throughput 6T SRAM-based Compute In-memory Design. / Kim, Minseo; Park, Jongsun.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 103-104 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, M & Park, J 2021, Short Word-Line Pulse with Fast Bit-Line Boosting for High Throughput 6T SRAM-based Compute In-memory Design. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 103-104, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 21/10/6. https://doi.org/10.1109/ISOCC53507.2021.9613869

Kim M, Park J. Short Word-Line Pulse with Fast Bit-Line Boosting for High Throughput 6T SRAM-based Compute In-memory Design. In Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 103-104. (Proceedings - International SoC Design Conference 2021, ISOCC 2021). doi: 10.1109/ISOCC53507.2021.9613869

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abstract = "In order to get over the read disturbance in SRAM-based Compute In-Memory (CIM), 6T SRAM bit-cell with underdrived Word-Line (WL) has been widely adopted. However, underdrived WL suffers from slower Bit-Line (BL) discharge, which eventually increases the CIM latency. In this paper, we propose a short WL pulse with fast BL boosting technique. Short WL pulse approach can efficiently reduce the read disturbance while BL is discharged through BL boosting circuit so that fast BL discharging time is guaranteed with little area overhead and higher reliability. 6T SRAM bit-cell array with BL boosting has been implemented in CMOS 28nm process, and the discharging time is decreased by 63.0% compared to the conventional WL underdrive technique.",

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Short Word-Line Pulse with Fast Bit-Line Boosting for High Throughput 6T SRAM-based Compute In-memory Design

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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