TY - JOUR
T1 - Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges
AU - Yang, Yejin
AU - Park, Young Soo
AU - Son, Jaemin
AU - Cho, Kyoungah
AU - Kim, Sangsig
N1 - Funding Information:
This research was supported in part by the Ministry of Trade, Industry & Energy (MOTIE; 10067791) and the Korea Semiconductor Research Consortium (KSRC) support program for the development of future semiconductor devices. It was also supported by a National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT; 2020R1A2C3004538), the Brain Korea 21 Plus Project of 2021 through the NRF funded by the Ministry of Science, ICT & Future Planning, and the Korea University Grant.
Publisher Copyright:
© 2021, The Author(s).
PY - 2021/12
Y1 - 2021/12
N2 - In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.
AB - In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.
UR - http://www.scopus.com/inward/record.url?scp=85115385117&partnerID=8YFLogxK
U2 - 10.1038/s41598-021-98182-7
DO - 10.1038/s41598-021-98182-7
M3 - Article
C2 - 34545175
AN - SCOPUS:85115385117
SN - 2045-2322
VL - 11
JO - Scientific reports
JF - Scientific reports
IS - 1
M1 - 18650
ER -