Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces

This article presents the use of pulse amplitude modulation four-level (PAM-4) transmitters (TXs) with pseudo-open drain (POD) termination for single-ended dynamic random access memory (DRAM) interfaces. To address the issues of increased power consumption and susceptibility to noise due to reduced signal-to-noise ratio (SNR), the use of data bus inversion (DBI) is implemented and investigated. By adopting the DBI technique in PAM-4 signaling, the driver power and supply fluctuations can be mitigated while preserving the pin overhead of one for the PAM-4-modulated DBI flag. On every single channel of the TX, the addition of a capacitive-coupled feed-forward equalizer (CC-FFE) is utilized to alleviate inter-symbol interference (ISI) effects. In addition, a reference impedance (ZQ) calibration method enabling the precise adjustment of ZQ values using variation-mitigated on-chip resistors is proposed. By utilizing the proposed ZQ calibration method, the driver's output impedance can be precisely adjusted under practical operating conditions while maintaining the off-chip cost for one reference resistor. The single-channel TX operates at data rates of up to 38 Gb/s while consuming 26.16 mW of power, which corresponds to a calculated energy efficiency of 0.688 pJ/bit. A 16.3% power dissipation reduction was measured in the drivers as a result of the PAM-4 DBI.