Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application

Jabeom Koo, Gil Su Kim, Junyoung Song, Kwan Weon Kim, Young Jung Choi, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm2 and 0.015mm2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.

Original languageEnglish
Title of host publication2009 IEEE Custom Integrated Circuits Conference, CICC '09
Pages717-720
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
Duration: 2009 Sept 132009 Sept 16

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
Country/TerritoryUnited States
CitySan Jose, CA
Period09/9/1309/9/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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