Abstract
Multicast on-chip communication is encountered in various cache-coherence protocols targeting multi-core processors, and its pervasiveness is increasing due to the proliferation of machine learning accelerators. In-network handling of multicast traffic imposes additional switching-level restrictions to guarantee deadlock freedom, while it stresses the allocation efficiency of Network-on-Chip (NoC) routers. In this work, we propose a novel NoC router microarchitecture, called SmartFork, which employs a versatile and cost-efficient multicast packet replication scheme that allows the design of high-throughput and low-cost NoCs. The design is adapted to the average branch splitting observed in real-world multicast routing algorithms. Compared to state-of-the-art NoC multicast approaches, SmartFork is demonstrated to yield higher performance in terms of latency and throughput, while still offering a cost-effective implementation.
| Original language | English |
|---|---|
| Title of host publication | 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728133201 |
| Publication status | Published - 2020 |
| Event | 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: 2020 Oct 10 → 2020 Oct 21 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Volume | 2020-October |
| ISSN (Print) | 0271-4310 |
Conference
| Conference | 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 |
|---|---|
| City | Virtual, Online |
| Period | 20/10/10 → 20/10/21 |
Bibliographical note
Publisher Copyright:© 2020 IEEE
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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